公开(公告)号：US20080132055A1

公开(公告)日：2008-06-05

申请号：US12016594

申请日：2008-01-18

申请人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

发明人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

IPC分类号： H01L21/4763

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

摘要翻译： 本发明提供了一种硬掩模，其位于具有嵌入其中的至少一个导电特征的低k电介质材料的表面上。 硬掩模包括邻近低k电介质材料的气密氧化物材料的下部区域，以及包含位于密封氧化物材料上方的Si，C和H原子的上部区域。 本发明还提供了制造本发明的硬掩模的方法以及形成包含该硬掩模的互连结构的方法。

公开(公告)号：US07335980B2

公开(公告)日：2008-02-26

申请号：US10981233

申请日：2004-11-04

申请人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

发明人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

IPC分类号： H01L23/12

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

摘要翻译： 本发明提供了一种硬掩模，其位于具有嵌入其中的至少一个导电特征的低k电介质材料的表面上。 硬掩模包括邻近低k电介质材料的气密氧化物材料的下部区域，以及包含位于密封氧化物材料上方的Si，C和H原子的上部区域。 本发明还提供了制造本发明的硬掩模的方法以及形成包含该硬掩模的互连结构的方法。

公开(公告)号：US07485582B2

公开(公告)日：2009-02-03

申请号：US12016594

申请日：2008-01-18

申请人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

发明人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

IPC分类号： H01L21/44

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

摘要翻译： 本发明提供了一种硬掩模，其位于具有嵌入其中的至少一个导电特征的低k电介质材料的表面上。 硬掩模包括邻近低k电介质材料的气密氧化物材料的下部区域，以及包含位于密封氧化物材料上方的Si，C和H原子的上部区域。 本发明还提供了制造本发明的硬掩模的方法以及形成包含该硬掩模的互连结构的方法。

公开(公告)号：US07456098B2

公开(公告)日：2008-11-25

申请号：US11403332

申请日：2006-04-13

申请人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

发明人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

IPC分类号： H01L21/4763

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械构造尖端。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US07067902B2

公开(公告)日：2006-06-27

申请号：US10726140

申请日：2003-12-02

申请人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

发明人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

IPC分类号： H01L29/40

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械的积累。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US07847402B2

公开(公告)日：2010-12-07

申请号：US11676522

申请日：2007-02-20

申请人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

发明人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

摘要翻译： 提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。 多个金属互连配线层嵌入在多个ILD层中。 介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。 介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。

公开(公告)号：US20080197513A1

公开(公告)日：2008-08-21

申请号：US11676522

申请日：2007-02-20

申请人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

发明人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

摘要翻译： 提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。 多个金属互连配线层嵌入在多个ILD层中。 介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。 介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。

公开(公告)号：US07678673B2

公开(公告)日：2010-03-16

申请号：US11832368

申请日：2007-08-01

申请人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

发明人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

IPC分类号： B05D3/12 ,  B05D3/06

CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

摘要翻译： 本发明提供了一种加强结构的方法，以治愈结构的缺陷，加强结构，从而加强电介质，而不影响结构的理想的低介电常数。 本发明的方法包括提供具有至少一个互连结构的半导体结构的步骤; 切割互连结构; 将至少一个渗透剂施加到所述互连结构中; 并渗透渗透剂渗透到互连结构中。

公开(公告)号：US20090035480A1

公开(公告)日：2009-02-05

申请号：US11832368

申请日：2007-08-01

申请人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

发明人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

IPC分类号： B05D3/12 ,  B05D3/06

CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

摘要翻译： 本发明提供了一种加强结构的方法，以治愈结构的缺陷，加强结构，从而加强电介质，而不影响结构的理想的低介电常数。 本发明的方法包括提供具有至少一个互连结构的半导体结构的步骤; 切割互连结构; 将至少一个渗透剂施加到所述互连结构中; 并渗透渗透剂渗透到互连结构中。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。