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公开(公告)号：US11138948B2
公开(公告)日：2021-10-05
申请号：US16623768
申请日：2019-12-03
Inventor： Tianhong Wang
IPC: G09G3/36
Abstract: A voltage stabilization circuit, a control method, and a display device are provided. The circuit includes first transistor, second transistor, and third transistor. A source of the first transistor is electrically connected to a drain of the second transistor and a gate of the third transistor, a drain of the first transistor is electrically connected to a first control output terminal of a power management integrated circuit, a gate of the first transistor is electrically connected to a second control output terminal of the power management integrated circuit, a gate of the second transistor is electrically connected to the second control output terminal of the power management integrated circuit, and a drain of the third transistor is electrically connected to a first level terminal for connecting to a display panel. This solves issues of VSSG potential drift caused by transistor aging and further guarantees normal operation of the display panel.
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公开(公告)号：US11335230B2
公开(公告)日：2022-05-17
申请号：US17053352
申请日：2020-08-04
Inventor： Tianhong Wang , Yunxiao Zhong , Ilgon Kim
IPC: G09G3/20
Abstract: The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.
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Patent Agency Ranking
公开(公告)号：US20220013056A1
公开(公告)日：2022-01-13
申请号：US17053352
申请日：2020-08-04
Inventor： Tianhong Wang , Yunxiao ZHONG , Ilgon KIM
IPC: G09G3/20
Abstract: The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.
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公开(公告)号：US11151959B2
公开(公告)日：2021-10-19
申请号：US16772647
申请日：2020-04-16
Inventor： Suping Xi , Tianhong Wang
IPC: G09G3/36
Abstract: A GOA circuit and a display panel are provided. In the GOA circuit, a first clock signal, a second clock signal, and a nth stage clock signal are separated into an input terminal of a first unit and an input terminal of a second unit. This reduces time that a thin film transistor in an inverter is subjected to forward current stress, thereby reducing offset of a threshold voltage of the thin film transistor, improving stability of the thin film transistor, and ensuring a normal output of a scan signal waveform.
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公开(公告)号：US11436990B2
公开(公告)日：2022-09-06
申请号：US16617168
申请日：2019-09-09
Inventor： Suping Xi , Tianhong Wang
IPC: G09G3/36
Abstract: A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.
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公开(公告)号：US11074884B1
公开(公告)日：2021-07-27
申请号：US16627298
申请日：2019-12-16
Inventor： Tianhong Wang , Suping Xi
Abstract: A control circuit and a display panel applied by the control circuit are provided. The control circuit includes a plurality of stages of shift registers, wherein each of the shift registers includes a first switch, wherein a control terminal of the first switch is configured to receive a first control signal, a first terminal of the first switch is configured to receive the first control signal, and a second terminal of the first switch is electrically coupled to a first node; a second switch, wherein a control terminal of the second switch is electrically coupled to the first node, a first terminal of the second switch is configured to receive a first clock signal, and a second terminal of the second switch is configured to receive a second control signal.
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公开(公告)号：US11609456B2
公开(公告)日：2023-03-21
申请号：US16960742
申请日：2020-04-28
Inventor： Pengpeng Xiong , Tianhong Wang
IPC: G02F1/1339 , G02F1/1335 , G03F7/00
Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer; a carrier of the first substrate includes a plurality of carriers, a spacer layer of the second substrate includes a plurality of spacers, each carrier disposed corresponds to each spacer, wherein the carrier comprises a base and at least one sub-carrier disposed on the base. The present disclosure adopts different thickness of the carriers to form a step difference, thereby relieving surface pressure of the display panel and saving manufacturing cost.
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