公开(公告)号：US11151959B2

公开(公告)日：2021-10-19

申请号：US16772647

申请日：2020-04-16

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Suping Xi ,  Tianhong Wang

IPC: G09G3/36

Abstract: A GOA circuit and a display panel are provided. In the GOA circuit, a first clock signal, a second clock signal, and a nth stage clock signal are separated into an input terminal of a first unit and an input terminal of a second unit. This reduces time that a thin film transistor in an inverter is subjected to forward current stress, thereby reducing offset of a threshold voltage of the thin film transistor, improving stability of the thin film transistor, and ensuring a normal output of a scan signal waveform.

公开(公告)号：US11436990B2

公开(公告)日：2022-09-06

申请号：US16617168

申请日：2019-09-09

Applicant: TCL China Star Optoelectronics Technology Co., Ltd.

Inventor： Suping Xi ,  Tianhong Wang

IPC: G09G3/36

Abstract: A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.

公开(公告)号：US11074884B1

公开(公告)日：2021-07-27

申请号：US16627298

申请日：2019-12-16

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Tianhong Wang ,  Suping Xi

IPC: G09G3/36 ,  G11C19/28

Abstract: A control circuit and a display panel applied by the control circuit are provided. The control circuit includes a plurality of stages of shift registers, wherein each of the shift registers includes a first switch, wherein a control terminal of the first switch is configured to receive a first control signal, a first terminal of the first switch is configured to receive the first control signal, and a second terminal of the first switch is electrically coupled to a first node; a second switch, wherein a control terminal of the second switch is electrically coupled to the first node, a first terminal of the second switch is configured to receive a first clock signal, and a second terminal of the second switch is configured to receive a second control signal.