公开(公告)号：US11645083B2

公开(公告)日：2023-05-09

申请号：US13974571

申请日：2013-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Shrey Sudhir Bhatia ,  Jeroen Vilegen

IPC: G06F9/38

CPC classification number: G06F9/3873 ,  G06F9/3838

Abstract: A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.