公开(公告)号：US20130244144A1

公开(公告)日：2013-09-19

申请号：US13887651

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Walter BLATCHFORD ,  Yong Seok CHOI ,  Thomas J. ATON

IPC: G03F1/38

CPC classification number: G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract translation: 形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。 相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。 相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。 相邻虚拟特征和最近的门级特征之间的间隔（i）维持栅极间距，或（ii）提供> = 2倍栅极间距的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。

公开(公告)号：US20130246983A1

公开(公告)日：2013-09-19

申请号：US13887672

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Walter BLATCHFORD ,  Yong Seok CHOI ,  Thomas J. ATON

IPC: G06F17/50

CPC classification number: G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.