Method of annealing out silicon defectivity
    1.
    发明公开

    公开(公告)号:US20230215737A1

    公开(公告)日:2023-07-06

    申请号:US17566942

    申请日:2021-12-31

    CPC classification number: H01L21/322 H01L21/76224

    Abstract: A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.

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