-
公开(公告)号：US20230006681A1
公开(公告)日：2023-01-05
申请号：US17931165
申请日：2022-09-12
Applicant: Texas Instruments Incorporated
Inventor： Shailesh Ganapat GHOTGALKAR , Wei FU , Venkatseema DAS , Jiankun HU
Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
-
公开(公告)号：US20210384913A1
公开(公告)日：2021-12-09
申请号：US17458001
申请日：2021-08-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailesh Ganapat GHOTGALKAR , Wei FU , Venkatseema DAS , Jiankun HU
Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
-
Search Results
2
records
(took 0.028 seconds)
