公开(公告)号：US20130316505A1

公开(公告)日：2013-11-28

申请号：US13951555

申请日：2013-07-26

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD, JR. ,  Yong Seok CHOI

IPC: H01L29/66

CPC classification number: H01L29/66484 ,  H01L21/28123 ,  H01L21/823828 ,  H01L27/0207 ,  H01L29/78

Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.

Abstract translation: 一种在集成电路中制造栅极电极和互连的方法，以及如此制造的集成电路，其具有改进的临界尺寸附近的栅极级互连的工艺裕度。 在深亚微米临界尺寸的光刻中使用的离轴照明通过具有在相同方向上具有优选取向的图案化特征促进，其间距限制在相对较窄的范围内。 在与栅极元件阵列平行的同一栅极级别（例如，“多晶”互连）的互连被放置在从栅极元件的端部指定的距离范围内，或者距离足以允许次级分辨率辅助 特征。

公开(公告)号：US20130244144A1

公开(公告)日：2013-09-19

申请号：US13887651

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Walter BLATCHFORD ,  Yong Seok CHOI ,  Thomas J. ATON

IPC: G03F1/38

CPC classification number: G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract translation: 形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。 相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。 相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。 相邻虚拟特征和最近的门级特征之间的间隔（i）维持栅极间距，或（ii）提供> = 2倍栅极间距的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。

公开(公告)号：US20130246983A1

公开(公告)日：2013-09-19

申请号：US13887672

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Walter BLATCHFORD ,  Yong Seok CHOI ,  Thomas J. ATON

IPC: G06F17/50

CPC classification number: G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.