公开(公告)号：US07543258B2

公开(公告)日：2009-06-02

申请号：US11402525

申请日：2006-04-11

申请人： Takeshi Kitahara ,  Yoshiki Tsukiboshi

发明人： Takeshi Kitahara ,  Yoshiki Tsukiboshi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5077 ,  G06F17/505 ,  G06F2217/62 ,  G06F2217/78

摘要： A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured to specify a part of the signal propagation paths as a circuit prevented from being changed. The clock tree synthesis section is configured to synthesize a clock tree of the semiconductor integrated circuit in accordance with the specification made by the prohibition specifying section.

摘要翻译： 时钟设计装置包括延迟时间调整部分，禁止指定部分和时钟树合成部分。 延迟时间调整部被配置为调整要设计的半导体集成电路上的信号传播路径的信号延迟时间。 禁止指定部分被配置为指定阻止改变的电路的一部分信号传播路径。 时钟树合成部分被配置为根据禁止指定部分制定的规范来合成半导体集成电路的时钟树。

公开(公告)号：US20060253821A1

公开(公告)日：2006-11-09

申请号：US11402525

申请日：2006-04-11

申请人： Takeshi Kitahara ,  Yoshiki Tsukiboshi

发明人： Takeshi Kitahara ,  Yoshiki Tsukiboshi

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/505 ,  G06F2217/62 ,  G06F2217/78

摘要： A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured to specify a part of the signal propagation paths as a circuit prevented from being changed. The clock tree synthesis section is configured to synthesize a clock tree of the semiconductor integrated circuit in accordance with the specification made by the prohibition specifying section.

公开(公告)号：US6074430A

公开(公告)日：2000-06-13

申请号：US955452

申请日：1997-10-21

申请人： Yoshiki Tsukiboshi

发明人： Yoshiki Tsukiboshi

IPC分类号： G06F17/50 ,  H01L27/118

CPC分类号： H01L27/118 ,  G06F17/5072

摘要： In a placing design employing standard cell system, a series of steps of merging, improving arraying in one-dimensional array and division are fundamentally alternately repeated to obtain a two-dimensional array of a plurality of cells which have relations interconnections. In the automatic cell placing method, since division is always performed after merging, placing obtained in the previous step can be corrected resulting in placing design having small dispersion in wiring density distribution.

摘要翻译： 在采用标准单元系统的放置设计中，一系列步骤的合并，改进了一维阵列和划分中的排列，从根本上交替重复，以获得具有关系互连的多个单元的二维阵列。 在自动电池放置方法中，由于在合并之后总是执行分割，所以可以校正在前一步骤中获得的放置，从而将具有小的色散的设计放置在布线密度分布中。