摘要:
Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.
摘要:
Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.
摘要翻译:本发明的示例性实施例涉及通过使用多相滤波器的低功率高精度无源多相时钟生成方案。 在提供半速率参考时钟的情况下,本发明的示例性实施例可以是基于低功率相位旋转器的25GB / s CDR架构。 它可能适用于多通道方案,并且并入具有提高的相位精度的相位内插器,以使奈奎斯特采样时钟相位。 为了提高相位精度,多相滤波器可用于将4相转换为8相,并内插相邻的45度相位。 通过使用陷波滤波器响应的特性,提出的谐波抑制多相滤波器(HRPPF)可以改善相位旋转器的线性度。
摘要:
Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.
摘要:
Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.
摘要:
Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.
摘要:
Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.
摘要翻译:本发明的示例性实施例涉及通过使用多相滤波器的低功率高精度无源多相时钟生成方案。 在提供半速率参考时钟的情况下,本发明的示例性实施例可以是基于低功率相位旋转器的25GB / s CDR架构。 它可能适用于多通道方案,并且并入具有提高的相位精度的相位内插器,以使奈奎斯特采样时钟相位。 为了提高相位精度,多相滤波器可用于将4相转换为8相,并内插相邻的45度相位。 通过使用陷波滤波器响应的特性,提出的谐波抑制多相滤波器(HRPPF)可以改善相位旋转器的线性度。
摘要:
Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.