公开(公告)号：US20220164411A1

公开(公告)日：2022-05-26

申请号：US17528472

申请日：2021-11-17

Applicant: Texas Instruments Incorporated

Inventor： Anshu Jain ,  Manu Mathew ,  Kumar Desappan ,  Anand Anil Pathak

IPC: G06F17/15 ,  G06F7/544 ,  G06F17/16 ,  G06N3/04

Abstract: In described examples, an integrated circuit includes a memory storing weights and biases, an N-bit fixed point matrix operations accelerator, and a processor. Starting with a first convolution layer, a convolution layer modeled using the processor receives input feature values. A feature scale and weight scale are reduced if an accumulator scale is greater than a maximum bias scale. The input feature values are rescaled using the feature scale, the weights are quantized using the weight scale, and the biases are quantized using the feature scale and weight scale. The rescaled input feature values and quantized weights and biases are convolved using the N-bit fixed point matrix operations accelerator to generate output feature values. The process repeats from the receive action using the output feature values as the input feature values of the next convolution layer. The process then repeats for all layers, feeding back an output feature range.