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公开(公告)号：US20180197067A1
公开(公告)日：2018-07-12
申请号：US15784588
申请日：2017-10-16
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Shyam Jagannathan , Manu Mathew , Jason T. Jones
Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.
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公开(公告)号：US20220101083A1
公开(公告)日：2022-03-31
申请号：US17035879
申请日：2020-09-29
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Shyam Jagannathan , Manu Mathew , Jason T. Jones
IPC: G06N3/04
Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.
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公开(公告)号：US10824934B2
公开(公告)日：2020-11-03
申请号：US15784588
申请日：2017-10-16
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Shyam Jagannathan , Manu Mathew , Jason T. Jones
Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.
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