公开(公告)号：US10397591B2

公开(公告)日：2019-08-27

申请号：US14684334

申请日：2015-04-11

Applicant: Texas Instruments Incorporated

Inventor： Dipan Kumar Mandal ,  Mihir Narendra Mody ,  Mahesh Madhukar Mehendale ,  Chaitanya Satish Ghone ,  Piyali Goswami ,  Naresh Kumar Yadav ,  Hetul Sanghvi ,  Niraj Nandan

IPC: H04N19/43 ,  H04N19/42 ,  H04N19/463 ,  G06F9/38

Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.

公开(公告)号：US20150296212A1

公开(公告)日：2015-10-15

申请号：US14684334

申请日：2015-04-11

Applicant: Texas Instruments Incorporated

Inventor： Dipan Kumar Mandal ,  Mihir Narendra Mody ,  Mahesh Madhukar Mehendale ,  Chaitanya Satish Ghone ,  Piyali Goswami ,  Naresh Kumar Yadav ,  Hetul Sanghvi ,  Niraj Nandan

IPC: H04N19/42 ,  G06F9/30 ,  H04N19/463 ,  G06F9/38

CPC classification number: H04N19/42 ,  G06F9/30181 ,  G06F9/3885 ,  H04N19/43 ,  H04N19/463

Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.

Abstract translation: 提供了一种用于视频编码解码引擎的控制处理器，其包括指令流水线。 指令流水线包括与指令存储器耦合以取指令的指令提取级，耦合到指令提取级以接收所取指令的指令解码级，以及耦合到指令解码级的接收和执行解码指令的执行级。 指令解码级和指令执行级被配置为解码和执行专门用于加速视频序列编码和编码视频位流解码的控制处理器的指令集中的一组指令。