公开(公告)号：US20240113102A1

公开(公告)日：2024-04-04

申请号：US17957931

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Guruvayurappan Mathur ,  Robert Oppen ,  Tawen Mei

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0629 ,  H01L29/66181 ,  H01L29/945

Abstract: A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.