公开(公告)号：US20020038415A1

公开(公告)日：2002-03-28

申请号：US10000667

申请日：2001-11-15

Applicant: U.S. Philips Corporation

Inventor： Frederik Zandveld ,  Marnix C. Vlot

IPC: G06F009/30

CPC classification number: G06F9/3804 ,  G06F12/0607

Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Abstract translation: 处理单元的指令被存储在多个存储体中，连续的指令被存储在连续的不同的存储体中。 无论何时开始执行指令，也开始读取将在多个指令周期后执行的一个指令。 因此，从不同的存储体并行地读取多个指令。 在读取指令之后，并且在开始执行指令之前，指令通过处理设备检测相关指令是否是分支指令的流水线。 如果是这样，则处理单元从分支目标指令开始并行地读取多条指令。 如果在稍后阶段出现分支，则所述指令数并行加载到管道中。