公开(公告)号：US12235950B2

公开(公告)日：2025-02-25

申请号：US17578292

申请日：2022-01-18

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  James Murray ,  Stefano Stabellini

IPC: G06F21/53 ,  G06F9/455

Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.

公开(公告)号：US11947459B2

公开(公告)日：2024-04-02

申请号：US17449561

申请日：2021-09-30

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  James Murray

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.