公开(公告)号：US20240281325A1

公开(公告)日：2024-08-22

申请号：US18111805

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Jonathan JASPER ,  Abbas MORSHED

IPC: G06F11/10 ,  G06F12/0871 ,  G06F12/0891

CPC classification number: G06F11/1068 ,  G06F12/0871 ,  G06F12/0891

Abstract: An integrated circuit (IC) device includes processor circuitry configured to output a first memory command having a first memory address, and in-line error correction control (ILECC) circuitry configured to receive the first memory command and output the first memory command to a memory device. The ILECC circuitry includes an error correction code (ECC) cache configured to store a first local ECC associated with the first memory command in a first cache line.