公开(公告)号：US20250124204A1

公开(公告)日：2025-04-17

申请号：US18381052

申请日：2023-10-17

Applicant: XILINX, INC.

Inventor： Pawan KULSHRESHTHA ,  Atul SRINIVASAN

IPC: G06F30/3312 ,  G06F30/31

Abstract: Performing timing analysis of a circuit design includes building a timing graph of the circuit design, and determining delays of devices and wires of the circuit design based on the timing graph. Further, clock and arrival propagations for the circuit design are performed based on the delays of the devices and wires, latch loops are identified in the circuit design, and latch analysis on latches of the latch loops is performed. The timing analysis further includes performing arrival propagation for circuit elements of the circuit design impacted by the latch analysis performed on the latches of the latch loops, performing latch analysis on latches of the circuit design external to the latch loops, and performing required time and slack calculations on the circuit design.