公开(公告)号：US20210159212A1

公开(公告)日：2021-05-27

申请号：US16694476

申请日：2019-11-25

Applicant: XILINX, INC.

Inventor： Jing JING ,  Shuxian WU ,  Xin X. WU ,  Yohan FRANS

IPC: H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L23/538 ,  H01L49/02 ,  H01L21/48 ,  H01L25/00

Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.