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1.发明授权Structure compatible with I2C bus and system management bus and timing buffering apparatus thereof 失效与I2C总线和系统管理总线及其定时缓冲装置兼容的结构公开(公告)号：US07752377B2
公开(公告)日：2010-07-06
申请号：US12015378
申请日：2008-01-16
申请人： Xiao-bing Zou , Shih-Hao Liu
发明人： Xiao-bing Zou , Shih-Hao Liu
IPC分类号： G06F13/36
CPC分类号： G06F13/4291
摘要： A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.
摘要翻译： 提供与I2C总线和系统管理（SM）总线兼容的结构。 该结构包括具有I2C总线接口的第一设备，具有SM总线接口的第二设备以及连接在I2C总线接口和SM总线接口之间的定时缓冲设备。 当第一设备向第二设备发送数据以便满足第二设备对数据保持时间的要求时，定时缓冲设备提供时间延迟。
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2.发明申请STRUCTURE COMPATIBLE WITH I2C BUS AND SYSTEM MANAGEMENT BUS AND TIMING BUFFERING APPARATUS THEREOF 失效结构兼容I2C总线和系统管理总线和时序缓冲器公开(公告)号：US20090119439A1
公开(公告)日：2009-05-07
申请号：US12015378
申请日：2008-01-16
申请人： Xiao-bing Zou , Shih-Hao Liu
发明人： Xiao-bing Zou , Shih-Hao Liu
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.
摘要翻译： 提供与I2C总线和系统管理（SM）总线兼容的结构。 该结构包括具有I2C总线接口的第一设备，具有SM总线接口的第二设备以及连接在I2C总线接口和SM总线接口之间的定时缓冲设备。 当第一设备向第二设备发送数据以便满足第二设备对数据保持时间的要求时，定时缓冲设备提供时间延迟。
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