公开(公告)号：US20240176652A1

公开(公告)日：2024-05-30

申请号：US18060438

申请日：2022-11-30

Applicant: Xilinx, Inc.

Inventor： Lucian Petrica ,  Kenneth O'Brien

IPC: G06F9/48 ,  G06F9/445 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/44505 ,  G06F9/544

Abstract: A system includes a network-on-chip (NoC). The system includes a protocol offload engine coupled to the NoC. The protocol offload engine is configured to generate packets of data for a selected protocol. The system includes a data movement processor coupled to the network-on-chip. The data movement processor is configured to receive a microcode instruction and, in response to the microcode instruction, establish data paths in the NoC that communicatively link a plurality of circuits involved in data transfers of a collective communication operation specified by the microcode instruction. The plurality of circuits include the protocol offload engine. The system includes a network transceiver coupled to the protocol offload engine. The network transceiver is configured to send the packets of data formatted by the protocol offload engine.