公开(公告)号：US11593547B1

公开(公告)日：2023-02-28

申请号：US17411484

申请日：2021-08-25

Applicant: Xilinx, Inc.

Inventor： Lucian Petrica ,  Mario Daniel Ruiz Noguera

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/347 ,  G06F30/34 ,  G06F111/04

Abstract: Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

公开(公告)号：US20230065842A1

公开(公告)日：2023-03-02

申请号：US17411484

申请日：2021-08-25

Applicant: Xilinx, Inc.

Inventor： Lucian Petrica ,  Mario Daniel Ruiz Noguera

IPC: G06F30/392 ,  G06F30/31

Abstract: Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

公开(公告)号：US20240176652A1

公开(公告)日：2024-05-30

申请号：US18060438

申请日：2022-11-30

Applicant: Xilinx, Inc.

Inventor： Lucian Petrica ,  Kenneth O'Brien

IPC: G06F9/48 ,  G06F9/445 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/44505 ,  G06F9/544

Abstract: A system includes a network-on-chip (NoC). The system includes a protocol offload engine coupled to the NoC. The protocol offload engine is configured to generate packets of data for a selected protocol. The system includes a data movement processor coupled to the network-on-chip. The data movement processor is configured to receive a microcode instruction and, in response to the microcode instruction, establish data paths in the NoC that communicatively link a plurality of circuits involved in data transfers of a collective communication operation specified by the microcode instruction. The plurality of circuits include the protocol offload engine. The system includes a network transceiver coupled to the protocol offload engine. The network transceiver is configured to send the packets of data formatted by the protocol offload engine.