公开(公告)号：US10756748B1

公开(公告)日：2020-08-25

申请号：US16396257

申请日：2019-04-26

Applicant: Xilinx, Inc.

Inventor： Prathamesh M. Khatavkar ,  John K. Jennings ,  Alonso Morgado

IPC: H03M1/12 ,  H03M1/46 ,  H03K5/24 ,  H01L29/94 ,  H03H19/00 ,  H01L49/02

Abstract: Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.