公开(公告)号：US20250004961A1

公开(公告)日：2025-01-02

申请号：US18344783

申请日：2023-06-29

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Kushagra Sharma ,  Surender Reddy Kisanagar

IPC: G06F13/28

Abstract: A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit implementing a plurality of data paths coupled to respective ones of the plurality of client circuits for conveying the read completion data as scheduled by the read scheduler circuit.