公开(公告)号：US10719464B1

公开(公告)日：2020-07-21

申请号：US16401104

申请日：2019-05-01

Applicant: Xilinx, Inc.

Inventor： Sunita Jain ,  Sweatha Rao

IPC: G06F13/362

Abstract: An example hardware accelerator in a computing system includes a bus interface coupled to a peripheral bus of the computing system; a lock circuit coupled to the bus interface; and a plurality of kernel circuits coupled to the lock circuit and the bus interface; wherein the plurality of kernel circuits provide lock requests to the lock circuit, the lock requests for data stored in system memory of the computing system; wherein the lock circuit is configured to process the lock requests from the plurality of kernel circuits and to issue atomic transactions over the peripheral bus through the bus interface based on the lock requests.