摘要:
A method for migrating volumes in a storage system includes identifying an extent of data (belonging to a volume) requiring migration from a source extent to a target extent. The method allocates a selected number of copiers to the extent of data to migrate the extent of data from the source extent to the target extent. Each copier is configured to copy a unit of data, which is a smaller division of the extent of data. The method monitors destages (i.e., writes) that occur to the source extent as the copiers migrate the extent of data from the source extent to the target extent. In the event the destages occur faster than the copiers can copy units to the target extent, the method allocates additional copiers to the extent of data to assist in migrating the extent of data. A corresponding apparatus and computer program product are also disclosed.
摘要:
A method for migrating volumes in a storage system includes identifying an extent of data (belonging to a volume) requiring migration from a source extent to a target extent. The method allocates a selected number of copiers to the extent of data to migrate the extent of data from the source extent to the target extent. Each copier is configured to copy a unit of data, which is a smaller division of the extent of data. The method monitors destages (i.e., writes) that occur to the source extent as the copiers migrate the extent of data from the source extent to the target extent. In the event the destages occur faster than the copiers can copy units to the target extent, the method allocates additional copiers to the extent of data to assist in migrating the extent of data. A corresponding apparatus and computer program product are also disclosed.
摘要:
In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要:
An apparatus for parity data management receives a write command and write data from a computing device. The apparatus also builds a parity control structure corresponding to updating a redundant disk array with the write data and stores the parity control structure in a persistent memory buffer of the computing device. The apparatus also updates the redundant disk array with the write data in accordance with a parity control map and restores the RAID controller parity map from the parity control structure as part of a data recovery operation if updating the redundant disk array with the write data is interrupted by a RAID controller failure resulting in a loss of the RAID controller parity map. In certain embodiments, the parity control structure is a RAID controller parity map.
摘要:
A method, system and program product save state data in a multi-processor system. A problem in the multi-processor system is detected and a statesave thread is spawned for each processor in the system. Each statesave thread directs a processor, in parallel with the other processors to attempt to identify a component in the system having a status of “incomplete”, indicating that state data of the component remains to be offloaded. When a component having a status of “incomplete” is identified, the processor executes statesave code to offload state data from the identified component. Upon completion of the state data offload from the identified component, the processor changes the status of the component to “complete”. The foregoing processes are repeated until no components are identified in the system having a status of “incomplete”.
摘要:
DMA mapping for adapters configured to communicate with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of the another group are overlayed in the DMA mapping space for control information for the respective adapters.
摘要:
A method, apparatus and program storage device for providing an anchor pointer in an operating system context structure for improving the efficiency of accessing thread specific data is provided. A kernel thread context structure is maintained in memory. A thread accesses a pointer memory in the kernel specific context structure and sets a value within the pointer memory that addresses data specific to the thread.
摘要:
In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要:
A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.
摘要:
A method, apparatus and program storage device that provides a user mode device interface for enabling software reuse. The user mode device interface allows device interface requests to be sent and received, including commands and data structures, via socket communication. A device state machine on the client side is implemented in a set of shared functions that can be incorporated by all applications that want to communicate to a particular service provider. The service provider offers the software functions over a user mode device interface via socket communication. The device state machine on the service provider side is embedded in the socket server implementation. The interaction between the state machines on both client and server sides ensures a device interface request is properly handled.