公开(公告)号：US07735028B2

公开(公告)日：2010-06-08

申请号：US11902050

申请日：2007-09-18

申请人： Yoshinori Soejima ,  Yoshikatsu Kouhara ,  Hiroaki Shiraishi ,  Kouichi Tanda ,  Takakazu Tokunaga ,  Koji Takatomi

发明人： Yoshinori Soejima ,  Yoshikatsu Kouhara ,  Hiroaki Shiraishi ,  Kouichi Tanda ,  Takakazu Tokunaga ,  Koji Takatomi

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).

摘要翻译： 允许计算机执行信息获取处理，获取表示在要重新设计的逻辑电路的每个块中提供的相应端口中使用的引脚的信息的文件和指示端口之间的连接关系的信息（＃2）。 执行多路复用器配置处理，其基于该文件，将块的输出端口的引脚分成小于引脚数的多个引脚组，并且配置具有复用从每个引脚输出的信号的功能的多路复用器 分为同一个针脚组（＃11，＃13）; 并且执行解复用器配置处理，其基于该文件，配置具有从多路复用器的多路复用器的多路复用器多路复用的多路复用器的输出端口输出的多路复用功能的解复用器，以及将各解复用信号输出到 各个输入目的地块（＃12，＃13）。

公开(公告)号：US20080077904A1

公开(公告)日：2008-03-27

申请号：US11902050

申请日：2007-09-18

申请人： Yoshinori Soejima ,  Yoshikatsu Kouhara ,  Hiroaki Shiraishi ,  Kouichi Tanda ,  Takakazu Tokunaga ,  Koji Takatomi

发明人： Yoshinori Soejima ,  Yoshikatsu Kouhara ,  Hiroaki Shiraishi ,  Kouichi Tanda ,  Takakazu Tokunaga ,  Koji Takatomi

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).

摘要翻译： 允许计算机执行信息获取处理，获取表示在要重新设计的逻辑电路的每个块中提供的相应端口中使用的引脚的信息的文件和指示端口之间的连接关系的信息（＃2）。 执行多路复用器配置处理，其基于该文件，将块的输出端口的引脚分成小于引脚数的多个引脚组，并且配置具有复用从每个引脚输出的信号的功能的多路复用器 分为同一个针脚组（＃11，＃13）; 并且执行解复用器配置处理，其基于该文件，配置具有对多路复用器的多路复用器多路复用的多路复用器的输出端口输出的信号进行解复用的解复用器，以及将各解复用信号输出到 各个输入目的地块（＃12，＃13）。

公开(公告)号：US07761822B2

公开(公告)日：2010-07-20

申请号：US12048668

申请日：2008-03-14

申请人： Koji Takatomi ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Takakazu Tokunaga

发明人： Koji Takatomi ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Takakazu Tokunaga

IPC分类号： G06F17/50

CPC分类号： G06F17/30067

摘要： A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated.

摘要翻译： 一种用于产生文件信息的方法和装置，包括设置有关速度转换电路块使用的时钟条件和时钟速度的时钟信息，重构包括用于容纳插入速度转换电路块的新时钟的时钟电路块，以及 将表示连接终端的连接关系的连接终端信息与具有设定的速度转换对象信息相关联，作为速度转换对象，需要连接速度转换的连接终端。 提取设置为速度转换对象的连接终端的连接终端信息，生成指示速度转换电路块中的连接端子的连接关系的速度转换电路信息和重建连接端子的连接关系的连接终端信息 ，并且生成在时钟电路块和接口块之间插入速度转换电路块的文件信息。

公开(公告)号：US08078423B2

公开(公告)日：2011-12-13

申请号：US11859040

申请日：2007-09-21

申请人： Takakazu Tokunaga ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Koji Takatomi

发明人： Takakazu Tokunaga ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Koji Takatomi

IPC分类号： G01R31/3183

CPC分类号： G01R31/318516 ,  G01R31/31717

摘要： A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

摘要翻译： 计算机终端检索与安装在电路板上的多个现场可编程门阵列的相应引脚相关的引脚数据。 计算机终端检索与连接检查相关的设置数据。 在检索引脚数据和设置数据后，计算机终端将连接检查的数据分配给可输出数据的所有引脚，每个引脚唯一的唯一数据。 计算机终端产生输入引脚数据并输出包含唯一数据的引脚数据，在其中存储输入引脚数据和输出引脚数据，并产生检查输出引脚和输入引脚之间的连接的检查电路。 计算机终端根据检查电路生成检查数据。

公开(公告)号：US20080235530A1

公开(公告)日：2008-09-25

申请号：US12048668

申请日：2008-03-14

申请人： Koji Takatomi ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Takakazu Tokunaga

发明人： Koji Takatomi ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Takakazu Tokunaga

IPC分类号： G06F1/08

CPC分类号： G06F17/30067

摘要： A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated.

摘要翻译： 一种用于产生文件信息的方法和装置，包括设置有关速度转换电路块使用的时钟条件和时钟速度的时钟信息，重构包括用于容纳插入速度转换电路块的新时钟的时钟电路块，以及 将表示连接终端的连接关系的连接终端信息与具有设定的速度转换对象信息相关联，作为速度转换对象，需要连接速度转换的连接终端。 提取设置为速度转换对象的连接终端的连接终端信息，生成指示速度转换电路块中的连接端子的连接关系的速度转换电路信息和重建连接端子的连接关系的连接终端信息 ，并且生成在时钟电路块和接口块之间插入速度转换电路块的文件信息。

公开(公告)号：US20080097717A1

公开(公告)日：2008-04-24

申请号：US11859040

申请日：2007-09-21

申请人： Takakazu Tokunaga ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Koji Takatomi

发明人： Takakazu Tokunaga ,  Kouichi Tanda ,  Hiroaki Shiraishi ,  Yoshikatsu Kouhara ,  Koji Takatomi

IPC分类号： G01R31/00

CPC分类号： G01R31/318516 ,  G01R31/31717

摘要： A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

摘要翻译： 计算机终端检索与安装在电路板上的多个现场可编程门阵列的相应引脚相关的引脚数据。 计算机终端检索与连接检查相关的设置数据。 在检索引脚数据和设置数据后，计算机终端将连接检查的数据分配给可输出数据的所有引脚，每个引脚唯一的唯一数据。 计算机终端产生输入引脚数据并输出包含唯一数据的引脚数据，在其中存储输入引脚数据和输出引脚数据，并产生检查输出引脚和输入引脚之间的连接的检查电路。 计算机终端根据检查电路生成检查数据。