公开(公告)号：US20070090872A1

公开(公告)日：2007-04-26

申请号：US11253673

申请日：2005-10-20

申请人： Yu-Chen Chen ,  Yao-Chun Lu

发明人： Yu-Chen Chen ,  Yao-Chun Lu

IPC分类号： G06G7/28

CPC分类号： H03H11/483 ,  H03L7/0891 ,  H03L7/093

摘要： A capacitance multiplier circuit for a filter is provided. The capacitance multiplier circuit capable of adjusting its equivalent capacitance and used in the filter, applied to a Phase Locked Loops (PLLs) circuit, includes a first operational amplifier having a positive input end for receiving an input signal, an output end, and a negative input end connected to the output end, a second operational amplifier having a positive input end, a negative input end connected to the output end of the first operational amplifier through a first resistor, and an output end connected to the negative input end through a second resistor, and a capacitor connected between the positive input end of the first operational amplifier and the output end of the second operational amplifier. An equivalent capacitance of the capacitance multiplier circuit is adjusted by configuring the ratio of the first resistor and the second resistor.

摘要翻译： 提供了一种用于滤波器的电容倍增器电路。 适用于锁相环（PLL）电路的能够调节其等效电容并用于滤波器的电容倍增器电路包括具有用于接收输入信号的正输入端，输出端和负极的第一运算放大器 连接到输出端的输入端，具有正输入端的第二运算放大器，通过第一电阻连接到第一运算放大器的输出端的负输入端，以及通过第二电阻连接到负输入端的输出端 电阻器和连接在第一运算放大器的正输入端和第二运算放大器的输出端之间的电容器。 通过配置第一电阻器和第二电阻器的比率来调节电容乘法器电路的等效电容。