公开(公告)号：US08401180B2

公开(公告)日：2013-03-19

申请号：US12053143

申请日：2008-03-21

申请人： Yuichi Komano ,  Hideo Shimizu ,  Koichi Fujisaki ,  Hideyuki Miyake ,  Atsushi Shimbo

发明人： Yuichi Komano ,  Hideo Shimizu ,  Koichi Fujisaki ,  Hideyuki Miyake ,  Atsushi Shimbo

IPC分类号： H04K1/00

CPC分类号： H04L9/0618 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/24

摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.

摘要翻译： 根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。 每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。

公开(公告)号：US20080292100A1

公开(公告)日：2008-11-27

申请号：US12053143

申请日：2008-03-21

申请人： Yuichi KOMANO ,  Hideo Shimizu ,  Koichi Fujisaki ,  Hideyuki Miyake ,  Atsushi Shimbo

发明人： Yuichi KOMANO ,  Hideo Shimizu ,  Koichi Fujisaki ,  Hideyuki Miyake ,  Atsushi Shimbo

IPC分类号： H04L9/06

CPC分类号： H04L9/0618 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/24

摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.

摘要翻译： 根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。 每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。

公开(公告)号：US20120307997A1

公开(公告)日：2012-12-06

申请号：US13585391

申请日：2012-08-14

申请人： Tsukasa Endo ,  Yuichi Komano ,  Koichi Fujisaki ,  Hideo Shimizu ,  Hanae Ikeda ,  Atsushi Shimbo

发明人： Tsukasa Endo ,  Yuichi Komano ,  Koichi Fujisaki ,  Hideo Shimizu ,  Hanae Ikeda ,  Atsushi Shimbo

IPC分类号： H04L9/28

CPC分类号： H04L9/0631 ,  H04L9/003

摘要： According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.

摘要翻译： 根据实施例，加密装置使用加密密钥进行加密处理，并从普通数据计算加密数据。 加密装置包括：寄存器; 输入单元，被配置为接收普通数据; 第一部分加密单元，被配置为从所述普通数据计算第一中间数据; 第二部分加密单元，被配置为基于第i个中间数据和加密密钥计算第（i + 1）个中间数据; 第一变换单元，被配置为：将第j个中间数据变换为第j变换数据; 并将第j个变换数据存储在寄存器中; 以及第二变换单元，被配置为将第j个变换后的数据变换为第j个中间数据; 第三部分加密单元，被配置为从第N个中间数据计算加密数据。 第二部分加密单元被配置为重复处理以计算（j + 1）中间数据，而j等于从1到N-1。

公开(公告)号：US09288040B2

公开(公告)日：2016-03-15

申请号：US13585391

申请日：2012-08-14

申请人： Tsukasa Endo ,  Yuichi Komano ,  Koichi Fujisaki ,  Hideo Shimizu ,  Hanae Ikeda ,  Atsushi Shimbo

发明人： Tsukasa Endo ,  Yuichi Komano ,  Koichi Fujisaki ,  Hideo Shimizu ,  Hanae Ikeda ,  Atsushi Shimbo

IPC分类号： H04L9/06 ,  H04L9/00

CPC分类号： H04L9/0631 ,  H04L9/003

摘要： According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.

摘要翻译： 根据实施例，加密装置使用加密密钥进行加密处理，并从普通数据计算加密数据。 加密装置包括：寄存器; 输入单元，被配置为接收普通数据; 第一部分加密单元，被配置为从所述普通数据计算第一中间数据; 第二部分加密单元，被配置为基于第i个中间数据和加密密钥计算第（i + 1）个中间数据; 第一变换单元，被配置为：将第j个中间数据变换为第j变换数据; 并将第j个变换数据存储在寄存器中; 以及第二变换单元，被配置为将第j个变换后的数据变换为第j个中间数据; 第三部分加密单元，被配置为从第N个中间数据计算加密数据。 第二部分加密单元被配置为重复处理以计算（j + 1）中间数据，而j等于从1到N-1。

公开(公告)号：US08909689B2

公开(公告)日：2014-12-09

申请号：US13361074

申请日：2012-01-30

申请人： Hideo Shimizu ,  Yuichi Komano ,  Koichi Fujisaki ,  Shinichi Kawamura

发明人： Hideo Shimizu ,  Yuichi Komano ,  Koichi Fujisaki ,  Shinichi Kawamura

IPC分类号： G06F7/72

CPC分类号： G06F7/728

摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.

摘要翻译： 根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。 第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。 加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果 量。 当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。

公开(公告)号：US20120131078A1

公开(公告)日：2012-05-24

申请号：US13361074

申请日：2012-01-30

申请人： Hideo Shimizu ,  Yuichi Komano ,  Koichi Fujisaki ,  Shinichi Kawamura

发明人： Hideo Shimizu ,  Yuichi Komano ,  Koichi Fujisaki ,  Shinichi Kawamura

IPC分类号： G06F7/523 ,  G06F7/50 ,  G06F5/01 ,  G06F7/48

CPC分类号： G06F7/728

摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.

摘要翻译： 根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。 第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。 加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果 量。 当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。

公开(公告)号：US08023643B2

公开(公告)日：2011-09-20

申请号：US11511401

申请日：2006-08-29

申请人： Koichi Fujisaki ,  Hideo Shimizu ,  Atsushi Shimbo

发明人： Koichi Fujisaki ,  Hideo Shimizu ,  Atsushi Shimbo

IPC分类号： H04L9/22

CPC分类号： H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/12

摘要： A first Exclusive OR circuit operates an Exclusive OR between input data and a predetermined random number. An operation circuit performs one operation of encryption and decryption of output data from the first Exclusive OR circuit. A data register circuit, which has a plurality of data hold units, holds data from the operation circuit in one data hold unit of the plurality of data hold units in response to a selection signal, and supplies the data from the one data hold unit to the operation circuit. A second Exclusive OR circuit performs an Exclusive OR between output data from the data register circuit and the random number. The operation circuit recursively performs the one operation of the data from the data register circuit and outputs next data to the data register circuit.

摘要翻译： 第一异或电路在输入数据和预定的随机数之间操作异或。 操作电路对来自第一异或电路的输出数据进行加密和解密的一个操作。 具有多个数据保持单元的数据寄存器电路响应于选择信号在多个数据保持单元的一个数据保持单元中保存来自运算电路的数据，并将来自一个数据保持单元的数据提供给 操作电路。 第二个异或电路在数据寄存器电路的输出数据和随机数之间执行异或运算。 运算电路从数据寄存器电路递归地执行数据的一次操作，并将下一个数据输出到数据寄存器电路。

公开(公告)号：US20070071235A1

公开(公告)日：2007-03-29

申请号：US11511401

申请日：2006-08-29

申请人： Koichi Fujisaki ,  Hideo Shimizu ,  Atsushi Shimbo

发明人： Koichi Fujisaki ,  Hideo Shimizu ,  Atsushi Shimbo

IPC分类号： H04L9/28

CPC分类号： H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/12

摘要： A first Exclusive OR circuit operates an Exclusive OR between input data and a predetermined random number. An operation circuit performs one operation of encryption and decryption of output data from the first Exclusive OR circuit. A data register circuit, which has a plurality of data hold units, holds data from the operation circuit in one data hold unit of the plurality of data hold units in response to a selection signal, and supplies the data from the one data hold unit to the operation circuit. A second Exclusive OR circuit performs an Exclusive OR between output data from the data register circuit and the random number. The operation circuit recursively performs the one operation of the data from the data register circuit and outputs next data to the data register circuit.

摘要翻译： 第一异或电路在输入数据和预定的随机数之间操作异或。 操作电路对来自第一异或电路的输出数据进行加密和解密的一个操作。 具有多个数据保持单元的数据寄存器电路响应于选择信号在多个数据保持单元的一个数据保持单元中保存来自运算电路的数据，并将来自一个数据保持单元的数据提供给 操作电路。 第二个异或电路在数据寄存器电路的输出数据和随机数之间执行异或运算。 运算电路从数据寄存器电路递归地执行数据的一次操作，并将下一个数据输出到数据寄存器电路。

公开(公告)号：US20110268266A1

公开(公告)日：2011-11-03

申请号：US13155889

申请日：2011-06-08

申请人： Koichi Fujisaki ,  Atsushi Shimbo

发明人： Koichi Fujisaki ,  Atsushi Shimbo

IPC分类号： H04L9/28

CPC分类号： H04L9/003 ,  H04L2209/046

摘要： According to one embodiment, a cryptographic processing apparatus is provided with first to fifth units. The first unit mask-converts input data from first temporary mask into first fixed mask (an invariable value in a first linear operation). In an encryption, the third unit performs a nonlinear operation on the mask-converted data and outputs a first result masked with second fixed mask data (an invariable value in a second linear operation). The fourth unit performs the second linear operation and outputs a encryption result masked with second fixed mask data. In a decryption, the second unit performs the first linear operation on the mask-converted data and outputs a second result masked with the first fixed mask. The third unit performs the nonlinear operation and outputs a decryption result masked with the second fixed mask. In encryption/decryptions, the fifth unit converts the mask of the encryption/decryption results into second temporary mask.

摘要翻译： 根据一个实施例，密码处理装置设置有第一至第五单元。 第一单元将输入数据从第一临时掩码转换为第一固定掩码（第一线性操作中的不变值）。 在加密中，第三单元对掩码转换数据执行非线性运算，并输出用第二固定掩码数据（第二线性运算中的不变值）屏蔽的第一结果。 第四单元执行第二线性操作并输出用第二固定掩码数据屏蔽的加密结果。 在解密中，第二单元对掩码转换数据执行第一线性操作，并输出用第一固定掩码屏蔽的第二结果。 第三单元执行非线性操作并输出用第二固定掩码屏蔽的解密结果。 在加密/解密中，第五单元将加密/解密结果的掩码转换为第二临时掩码。

公开(公告)号：US07869592B2

公开(公告)日：2011-01-11

申请号：US12285077

申请日：2008-09-29

申请人： Koichi Fujisaki ,  Atsushi Shimbo

发明人： Koichi Fujisaki ,  Atsushi Shimbo

IPC分类号： H04K1/00

CPC分类号： H04L9/0631 ,  H04L2209/122 ,  H04L2209/125

摘要： A calculation apparatus capable of executing any of a first calculating process operation including a first matrix calculation, and a second calculating process operation including a second matrix calculation, includes: a first calculation unit for executing the second matrix calculation; at least one calculation unit other than the first calculation unit, for executing a matrix calculation in parallel to the first calculation unit so as to execute the first matrix calculation; and a logic circuit for performing a logic calculation with respect to a calculation result of the first calculation unit and a calculation result of the other calculation unit. Then, when a calculation result of the first matrix calculation is requested, the calculation apparatus acquires the calculation result from the logic circuit. As a result, the calculation apparatus and an encrypt/decrypt processing apparatus can commonly perform portions of the plural calculating process operations which contain the matrix calculations, and can realize high speed operation by executing portions of the matrix calculations in parallel.

摘要翻译： 一种能够执行包括第一矩阵计算的第一计算处理操作和包括第二矩阵计算的第二计算处理操作中的任一者的计算装置，包括：第一计算单元，用于执行第二矩阵计算; 至少一个除第一计算单元之外的计算单元，用于与第一计算单元并行地执行矩阵计算，以便执行第一矩阵计算; 以及用于对第一计算单元的计算结果执行逻辑运算的逻辑电路和另一个计算单元的计算结果。 然后，当请求第一矩阵计算的计算结果时，计算装置从逻辑电路获取计算结果。 结果，计算装置和加密/解密处理装置可以共同执行包含矩阵计算的多个计算处理操作的部分，并且可以通过并行执行矩阵计算的部分来实现高速操作。