公开(公告)号：US20180292458A1

公开(公告)日：2018-10-11

申请号：US15482336

申请日：2017-04-07

申请人： Hamilton Sundstrand Corporation

发明人： Kirk A. Lillestolen ,  Kanwalpreet Reen

IPC分类号： G01R31/3185 ,  G06F11/25

CPC分类号： G01R31/318597 ,  G01R31/31719 ,  G01R31/318544 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318588 ,  G06F11/25 ,  G06F21/85

摘要： A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a multi-channel unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the multi-channel unlock sequence via two or more unlock channels, determine, via an unlock logic, whether the execution of the multi-channel unlock sequence is valid, and responsive to determining that the execution of the multi-channel unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

公开(公告)号：US10078112B2

公开(公告)日：2018-09-18

申请号：US15236182

申请日：2016-08-12

申请人： mCube Inc.

发明人： Sanjay Bhandari ,  Tony Maraldo

IPC分类号： G06F21/00 ,  G01R31/317 ,  G01R31/3177 ,  G06F21/73

CPC分类号： G01R31/31719 ,  G01R31/31701 ,  G01R31/3177 ,  G06F21/73 ,  G06F2221/2149

摘要： A method is provided for implementing a security mechanism in an integrated MEMS (Micro-Electro-Mechanical-System) device having a MEMS sensor with an output register associated with a sensing operation, the integrated MEMS device being electrically coupled to a computing system programmed to perform the method. The method includes, in normal operation, reading from the output register an output of the sensing operation, and in a test mode, determining, by a processor disposed within the computing system, a random value. Determining the random value can include reading from the output register, which in the test mode or provides a value from an internal pattern generator. The method also includes determining, by the processor, a validation value, reading, by the processor, the random value stored in the output register; and determining, by the processor, whether the integrated device is valid using the validation value and the random value stored in the output register.

公开(公告)号：US10012693B2

公开(公告)日：2018-07-03

申请号：US15273869

申请日：2016-09-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minsoo Lim ,  Sungjae Lee

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185

CPC分类号： G01R31/31705 ,  G01R31/31719 ,  G01R31/3177 ,  G01R31/318588

摘要： A system on chip (SoC) is provided. The system on chip includes a multiprocessor that includes multiple processors, a debugging controller that includes a debug port and retention logic configured to store an authentication result of a secure joint test action group system, and a power management unit configured to manage power supplied to the multiprocessor and the debugging controller. The power management unit changes the debug port and the retention logic into an alive power domain in response to a debugging request signal.

公开(公告)号：US09970986B2

公开(公告)日：2018-05-15

申请号：US14640180

申请日：2015-03-06

申请人： Cryptography Research, Inc.

发明人： Craig E. Hampel ,  Scott C. Best

IPC分类号： G11C5/14 ,  G01R31/317 ,  G06F21/73 ,  G01R31/30

CPC分类号： G01R31/31719 ,  G01R31/3008 ,  G06F21/73

摘要： Systems and methods for authenticating integrated circuits. An example integrated circuit may comprise: a plurality of functional units electrically coupled to a power source; and an authenticating circuit comprising a plurality of voltage measurement units, each voltage measurement unit to measure, at one or more frequencies over one or more periods of time, a local voltage at a respective functional unit of the plurality of functional units.

公开(公告)号：US09939074B2

公开(公告)日：2018-04-10

申请号：US14913615

申请日：2014-08-06

申请人： Telefonaktiebolaget LM Ericsson (Publ)

发明人： Peter Svensson

IPC分类号： H04L29/00 ,  F16K25/04 ,  B01J8/00 ,  F16K3/02 ,  F16K27/04

CPC分类号： F16K25/04 ,  B01J8/0015 ,  B01J2208/00548 ,  B01J2208/00787 ,  F16K3/02 ,  F16K27/044 ,  G01R31/31719 ,  G01R31/318588

摘要： Secured debug of an integrated circuit having a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit, a test interface through which the test operation mode is controllable, an on-chip memory which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive an authenticated object through the test interface, and store the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure to determine that the authenticated object is available in the on-chip memory, authenticate the authenticated object, and—upon successful authentication—render the more protected resources accessible to a debug host external to the integrated circuit.

公开(公告)号：US09927486B2

公开(公告)日：2018-03-27

申请号：US15241805

申请日：2016-08-19

申请人： UltraSoC Technologies Ltd.

发明人： Andrew Brian Thomas Hopkins ,  Arnab Banerjee ,  Stephen John Barlow ,  Klaus Dieter Mcdonald-Maier

IPC分类号： G06F12/00 ,  G11C7/00 ,  G01R31/28 ,  G01R31/317 ,  G06F21/44 ,  G06F21/62 ,  G06F21/85 ,  G06F11/34

CPC分类号： G01R31/2884 ,  G01R31/31705 ,  G01R31/31719 ,  G06F11/27 ,  G06F11/348 ,  G06F21/44 ,  G06F21/62 ,  G06F21/85 ,  G06F2201/835 ,  G06F2201/86 ,  G06F2201/88

摘要： Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

公开(公告)号：US09898625B2

公开(公告)日：2018-02-20

申请号：US14727299

申请日：2015-06-01

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Alfredo Olmos ,  James R. Feddeler ,  Miten H. Nagda ,  Stefano Pietri

IPC分类号： G01R11/24 ,  G06F21/81 ,  G06F1/28 ,  G06F1/14 ,  G01R31/317

CPC分类号： G06F21/81 ,  G01R31/31719 ,  G06F1/14 ,  G06F1/28

摘要： A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

公开(公告)号：US09891277B2

公开(公告)日：2018-02-13

申请号：US14502406

申请日：2014-09-30

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Joel R. Knight ,  James B. Eifert ,  Stefano Pietri ,  Steven K. Watkins

IPC分类号： G01R31/28 ,  G01R31/317

CPC分类号： G01R31/31719 ,  G01R31/31701

摘要： An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.

公开(公告)号：US20180004944A1

公开(公告)日：2018-01-04

申请号：US15543501

申请日：2016-01-12

申请人： NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITY ,  TELECOM PARISTECH

发明人： Makoto NAGATA ,  Jean-Luc DANGER ,  Daisuke FUJIMOTO ,  Shivam BHASIN

IPC分类号： G06F21/55 ,  G01R31/28

CPC分类号： G06F21/556 ,  G01R31/2884 ,  G01R31/31719 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04 ,  H04L9/10

摘要： Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented.

公开(公告)号：US20170244549A1

公开(公告)日：2017-08-24

申请号：US15439578

申请日：2017-02-22

申请人： ESHARD

发明人： Hugues THIEBEAULD DE LA CROUEE ,  Georges GAGNEROT

IPC分类号： H04L9/00

CPC分类号： H04L9/003 ,  G01R31/31719 ,  G06F21/72 ,  G06F21/75 ,  G09C1/00 ,  H04L9/002 ,  H04L9/3242 ,  H04L9/3247 ,  H04L9/3249 ,  H04L9/3252 ,  H04L2209/08 ,  H04L2209/12

摘要： A test method for a circuit can include: acquiring a plurality of value sets including values corresponding to activity of the circuit when the circuit executes an operation of an operation set of distinct cryptographic operations applied to a same secret data, selecting at least two subsets of values in each value set, for each value set and each value subset, counting occurrence numbers of values transformed by a respective first surjective function applied to the values of the subset, for each value set, forming all possible n-tuples associating together one of the occurrence numbers of each value subset of the value set, and computing a combined occurrence number for each n-tuple of the value set by multiplying together the occurrence numbers associated by the n-tuple, to form an occurrence number set for the value set, for each operation of the operation set, and each possible value of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets, obtained by adding together the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value of the possible values of the secret data part, provide a partial operation result having a same transformed value by a second surjective function, and analyzing the cumulative occurrence number sets to determine the part of the secret data.