公开(公告)号：US10014034B2

公开(公告)日：2018-07-03

申请号：US15286836

申请日：2016-10-06

申请人： Micron Technology, Inc.

发明人： Jeremiah J. Willcock ,  Glen E. Hush

IPC分类号： G11C7/02 ,  G11C7/06

CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2211/4013

摘要： The present disclosure is related to shifting data using sensing circuitry. An example apparatus can include a first sensing component and a second sensing component. The first sensing component can include a first sense amplifier coupled to a first pair of complementary sense lines and a first compute component comprising a number of first pass transistors. The second sensing component can include a second sense amplifier coupled to a second pair of complementary sense lines. The second sensing component can include a second compute component comprising a number of second pass transistors. The first pair of complementary sense lines can be coupled to the number of first pass transistors and the number of second pass transistors.

公开(公告)号：US20170365300A1

公开(公告)日：2017-12-21

申请号：US15647166

申请日：2017-07-11

申请人： Cypress Semiconductor Corporation

发明人： Kobi Danon ,  Yoram Betser ,  Alex Kushnarenko

IPC分类号： G11C7/06

CPC分类号： G11C7/062 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/4013

摘要： Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed the result of a complementary read is output for each bit of the data word.

公开(公告)号：US09711715B2

公开(公告)日：2017-07-18

申请号：US15189114

申请日：2016-06-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen Heinrich-Barna

IPC分类号： G11C11/22 ,  H01L43/12 ,  H01L21/66 ,  H01L27/115

CPC分类号： H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

摘要： Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

公开(公告)号：US20170162234A1

公开(公告)日：2017-06-08

申请号：US14961484

申请日：2015-12-07

申请人： GLOBALFOUNDRIES INC.

发明人： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC分类号： G11C7/06 ,  G11C7/18 ,  G11C5/14 ,  G11C7/12

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

摘要： A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

公开(公告)号：US20170092359A1

公开(公告)日：2017-03-30

申请号：US14867308

申请日：2015-09-28

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： G11C15/04 ,  H01L27/108

CPC分类号： G11C15/04 ,  G11C11/404 ,  G11C15/046 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/10802

摘要： A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

公开(公告)号：US09349490B2

公开(公告)日：2016-05-24

申请号：US14597824

申请日：2015-01-15

申请人： STMICROELECTRONICS S.r.l.

发明人： Marcella Carissimi ,  Marco Pasotti

IPC分类号： G11C29/00 ,  G11C29/52 ,  G11C7/18 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  G06F11/10

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C7/18 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/4013

摘要： A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.

摘要翻译： 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。

公开(公告)号：US20150212880A1

公开(公告)日：2015-07-30

申请号：US14597824

申请日：2015-01-15

申请人： STMICROELECTRONICS S.r.l.

发明人： Marcella CARISSIMI ,  Marco PASOTTI

IPC分类号： G06F11/10 ,  G11C29/52

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C7/18 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/4013

摘要： A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.

摘要翻译： 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。

公开(公告)号：US20130286716A1

公开(公告)日：2013-10-31

申请号：US13900392

申请日：2013-05-22

申请人： Robert Newton Rountree

发明人： Robert Newton Rountree

IPC分类号： G11C8/08 ,  G11C11/418 ,  G11C11/408

CPC分类号： G11C8/08 ,  G11C5/063 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/418 ,  G11C11/419 ,  G11C2211/4013

摘要： A method of operating a memory circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals. A first part (714) of the plurality of columns is selected in response to a first voltage applied to the selected word line. A second part (716) of the plurality of columns is selected in response to a second voltage applied to the selected word line.

摘要翻译： 公开了一种操作与动态随机存取存储器（DRAM）和静态随机存取存储器（SRAM）兼容的存储器电路的方法。 该方法包括响应于多个行地址信号选择连接到行存储器单元的字线（708），并且响应于多个列地址信号选择存储器单元的多个列（706,710）。 响应于施加到所选择的字线的第一电压来选择多个列的第一部分（714）。 响应于施加到所选字线的第二电压来选择多个列的第二部分（716）。

公开(公告)号：US20110261633A1

公开(公告)日：2011-10-27

申请号：US12662533

申请日：2010-04-21

申请人： Vikas Chandra ,  Cezary Pietrzyk ,  Robert Campbell Aitken

发明人： Vikas Chandra ,  Cezary Pietrzyk ,  Robert Campbell Aitken

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/413 ,  G11C2211/4013

摘要： An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells. If, at a time of the read operation, one of the at least three memory cells holds a complement value of the written data value, the voltage of the shared bit line nonetheless has a value such that the read data value is determined with the same value as the written data value.

摘要翻译： 提供了集成电路，其包括具有多行存储器单元和多列位单元的至少一个存储单元阵列。 存储单元的每一列耦合到多个位线中的一个。 存储单元的每行被耦合到多个字线之一，以根据相应的字线信号来控制该行存储单元与多个位线的耦合。 字线驱动器电路被配置为将至少三行存储器单元的字线组合在一起，使得至少三行存储器单元的字线共享公共字线信号。 因此，在写入操作中，将写入存储器单元阵列的写入数据值写入至少三个具有共享位线的存储单元。 读取电路耦合到多个位线，被配置为使得在读取操作中，至少三个存储器单元通过公共字线信号都耦合到共享位线，读取数据值被确定 取决于存储在至少三个存储器单元中的数据值，依赖于共享位线的电压。 如果在读取操作时，至少三个存储器单元中的一个存储器单元保持写入的数据值的补码值，则共享位线的电压仍然具有使得读取的数据值被确定为相同的值 值作为写入数据值。

公开(公告)号：US20100259975A1

公开(公告)日：2010-10-14

申请号：US12823973

申请日：2010-06-25

申请人： Haruki TODA

发明人： Haruki TODA

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C5/02 ,  G11C7/18 ,  G11C13/0007 ,  G11C2211/4013 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.

摘要翻译： 存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线沿着第一方向布置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。