公开(公告)号：US20140040700A1

公开(公告)日：2014-02-06

申请号：US13877650

申请日：2011-10-04

申请人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

发明人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

IPC分类号： G06F11/10

CPC分类号： G06F11/1044 ,  G06F5/015 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/1145 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/2978 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6566 ,  H03M13/6569 ,  H03M13/6577

摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

摘要翻译： 在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。 可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。 利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

公开(公告)号：US08214723B2

公开(公告)日：2012-07-03

申请号：US12223109

申请日：2007-01-18

申请人： Jean-Baptiste Dore ,  Marie-Hélène Hamon ,  Pierre Penard

发明人： Jean-Baptiste Dore ,  Marie-Hélène Hamon ,  Pierre Penard

IPC分类号： H03M13/00

CPC分类号： H03M13/2972 ,  H03M13/1194 ,  H03M13/2771 ,  H03M13/2978 ,  H03M13/6566

摘要： A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).

摘要翻译： 一种输入比特序列（S0）的低延迟编码以产生编码比特序列（S）的方法和相应的解码方法，所述编码方法包括：第一编码步骤（E1），其应用于输入比特序列 （S0），使用第一代码; 交织步骤（E3），其中交织器交织从所述第一码获得的比特; 以及使用第二代码应用于从所述交织器获得的比特的奇偶校验第二编码步骤（E4），以生成所述编码比特序列（S）。 奇偶校验第二编码步骤（E4）在预定数量＆Dgr之后开始; 的位已被交织，所述预定数量＆Dgr; 根据所述交织步骤（E3）的一个或多个参数和与在所述交织步骤期间要处理的总位数相对应的比特的第一较高数目＆Dgr比特，位于第一较低数字＆amp; （E3）。

公开(公告)号：US20100070826A1

公开(公告)日：2010-03-18

申请号：US12306637

申请日：2007-06-14

申请人： Andrea Ancora ,  Giuseppe Montalbano

发明人： Andrea Ancora ,  Giuseppe Montalbano

IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/05

CPC分类号： H03M13/29 ,  H03M13/2978 ,  H03M13/45

摘要： The invention related to a turbo decoder comprising SISO decoding modules each other interconnected in a feedback control scheme having scaling modules for applying a scaling factor to extrinsic information delivered by said SISO decoding modules. The turbo decoder comprises a selection module for adaptively selecting said scaling factor based on a number of decoding iterations of the turbo decoder.

摘要翻译： 本发明涉及一种包括SISO解码模块的turbo解码模块，其在具有缩放模块的反馈控制方案中相互连接，该缩放模块用于将缩放因子应用于由所述SISO解码模块传送的外部信息。 turbo解码器包括一个选择模块，用于根据turbo解码器的解码迭代次数自适应地选择所述缩放因子。

公开(公告)号：US07440521B2

公开(公告)日：2008-10-21

申请号：US09952212

申请日：2001-09-12

申请人： Hau Thien Tran ,  Kelly B. Cameron

发明人： Hau Thien Tran ,  Kelly B. Cameron

IPC分类号： H03D1/00

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： In a normalization process, overflow occurring in limited size registers, holding the alpha or beta values in a map decoder, may be overcome by subtracting a constant value from all of the alpha or beta values when they reach a limit. Because subtracting a constant value may slow down the computation, detection of a constant value may occur on one decoding cycle and normalization on the succeeding decoding cycle. A multiplexor type circuit can be used to direct either zeros, in the normalization case, or a most significant bit(s), in computations without normalization, into the register holding the alpha or beta values. To minimize the impact on the computation by the normalization process, the multiplexor circuit can be set by the previous decoder cycle so that the computation does not have to wait for the multiplexor to be set to normalization or normal computation.

摘要翻译： 在归一化过程中，通过在映射解码器中保持α或β值的有限大小的寄存器中发生的溢出可以通过在达到极限时从所有α或β值中减去常数值来克服。 因为减去常数值可能会减慢运算，所以在一个解码周期可能发生常数值的检测，并在随后的解码周期进行归一化。 多路复用器类型电路可以用于在没有规范化的计算中将标准化情况下的零或最高有效位引导到保存α或β值的寄存器中。 为了最小化通过归一化处理对计算的影响，可以通过先前的解码器周期来设置多路复用器电路，使得计算不必等待多路复用器被设置为归一化或正常计算。

公开(公告)号：US07421034B2

公开(公告)日：2008-09-02

申请号：US10843606

申请日：2004-05-11

申请人： Kelly B. Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas Ashford Hughes, Jr.

发明人： Kelly B. Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas Ashford Hughes, Jr.

IPC分类号： H04L5/12 ,  H04L23/02

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已经编码的数据序列，例如由Reed-Soloman编码器提供的。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US07409006B2

公开(公告)日：2008-08-05

申请号：US11481365

申请日：2006-07-05

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

IPC分类号： H04L27/00

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US07242726B2

公开(公告)日：2007-07-10

申请号：US09878148

申请日：2001-06-08

申请人： Kelly B. Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas Ashford Hughes, Jr.

发明人： Kelly B. Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas Ashford Hughes, Jr.

IPC分类号： H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已经编码的数据序列，例如由Reed-Soloman编码器提供的。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US07200798B2

公开(公告)日：2007-04-03

申请号：US10608831

申请日：2003-06-26

申请人： Mark Andrew Bickerstaff

发明人： Mark Andrew Bickerstaff

IPC分类号： H03M13/03

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/2972 ,  H03M13/2978 ,  H03M13/395 ,  H03M13/6511

摘要： A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.

摘要翻译： 具有两种操作模式的turbo解码器根据N状态的基数K格网解码接收到的信息，其中N和K是等于1或更大的整数。 turbo解码器使用在线寻址技术，其允许其在第一操作模式中作为串行卷积码解码器操作，并且在第二操作模式中使用并行卷积码解码器。 解码器使用在线寻址技术，允许它在处理接收到的信息时使用相同的存储器块来存储和检索格状态。 turbo解码器也可以按照N状态的基数K网格进行操作，其中N是等于2或更大的整数，K是等于4或更大的整数。

公开(公告)号：US20060265635A1

公开(公告)日：2006-11-23

申请号：US11232361

申请日：2005-09-21

申请人： Atsuko Tokita ,  Hidetoshi Shirasawa ,  Masakazu Harata

发明人： Atsuko Tokita ,  Hidetoshi Shirasawa ,  Masakazu Harata

IPC分类号： H03M13/03

CPC分类号： H03M13/3972 ,  H03M13/2957 ,  H03M13/2978

摘要： When an information length N is divided by a division length L, if the number of divisions including the remainder is 2n, then backward probabilities are calculated from the Nth backward probability in the reverse direction to the (n+1)th section and backward probabilities at division points are stored as discrete values, and in parallel with these backward probability calculations, forward probabilities are calculated from the first forward probability in the forward direction to the nth section and the forward probabilities at division points are stored as discrete values. Subsequently, the backward probabilities and forward probabilities stored as discrete values are used to calculate backward probabilities and forward probabilities for each section, and using these probabilities, decoding results are calculated in sequence for all sections.

摘要翻译： 当信息长度N除以分割长度L时，如果包括余数的分割数为2n，则从与第（n + 1）部分相反的第N个后向概率计算后向概率，并且反向概率 在分割点被存储为离散值，并且与这些后向概率计算并行地，从向前方向的第一前向概率到第n个部分计算前向概率，并将分割点处的前向概率存储为离散值。 随后，使用作为离散值存储的反向概率和向前概率来计算每个部分的后向概率和向前概率，并且使用这些概率，对于所有部分按顺序计算解码结果。

公开(公告)号：US07120851B2

公开(公告)日：2006-10-10

申请号：US10649785

申请日：2003-08-28

申请人： Yu Jing Ting ,  Noriyoshi Ito ,  Hiroshi Katsuragawa

发明人： Yu Jing Ting ,  Noriyoshi Ito ,  Hiroshi Katsuragawa

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： H03M13/3927 ,  H03M13/2978

摘要： The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.

摘要翻译： 本发明一般涉及纠错编码，更具体地说，涉及用于级联码（例如，turbo码）的解码器。 本发明提供了一种用于对编码数据进行解码的解码器，该解码器包括：一个处理器，具有一个输入，该输入接收一个符号块的概率估计，并且被配置为在下一个迭代状态下计算所述符号的概率估计; 规范化所述下一状态估计的正规化装置; 接收所述归一化和所述非标准化下一状态估计的开关，所述开关的输出耦合到所述处理器的输入; 其中所述开关被布置为根据迭代状态在归一化和非标准化的下一状态估计之间切换。