High-speed RFID circuit placement method and device
    91.
    发明授权
    High-speed RFID circuit placement method and device 有权
    高速RFID电路放置方法及装置

    公开(公告)号:US07623034B2

    公开(公告)日:2009-11-24

    申请号:US11148676

    申请日:2005-06-09

    IPC分类号: G08B13/14

    摘要: A high-speed machine and method for placing an RFID circuit onto an electrical component includes separating an RFID circuit from a web of RFID circuits, and placing the RFID circuit onto an electrical component with a placing device. The separating includes directing the RFID circuit onto a transfer drum of the placement device and separably coupling the RFID circuit to the transfer drum. According to one method, a separator device separates and directs chips or interposers onto a placement device. According to another method, chips or interposers are tested before being separated from a web, and if good, are separated from the web, directed onto a placement device, and placed on an electrical component. If defective, the chips or interposers are not directed onto a placement device and are removed by a scrap web removal device.

    摘要翻译: 用于将RFID电路放置在电气部件上的高速机器和方法包括将RFID电路与RFID电路的网络分开,并将RFID电路放置在具有放置装置的电气部件上。 分离包括将RFID电路引导到放置装置的转印鼓上,并将RFID电路可分离地耦合到转印鼓上。 根据一种方法,分离器装置将芯片或插入件分离并引导到放置装置上。 根据另一种方法,在与纸幅分离之前测试芯片或插入物,并且如果良好,则从纸幅分离,被引导到放置装置上并放置在电气部件上。 如果有缺陷,则芯片或插入件不被引导到放置装置上,并且被废料网移除装置移除。

    SYSTEMS AND METHODS FOR DISTRIBUTING AND MANAGING VIRTUAL MACHINES
    92.
    发明申请
    SYSTEMS AND METHODS FOR DISTRIBUTING AND MANAGING VIRTUAL MACHINES 有权
    用于分布和管理虚拟机的系统和方法

    公开(公告)号:US20090204961A1

    公开(公告)日:2009-08-13

    申请号:US12029637

    申请日:2008-02-12

    IPC分类号: G06F9/455

    CPC分类号: G06F8/60 G06F9/455

    摘要: An embodiment relates generally to a method of distributing virtual machines. The method includes specifying a set of requirements for a virtual machine and instantiating a virtual machine based on a lightweight reusable profile, based on the set of requirements as described in the profile. The method also includes importing the profile to a distribution server; and distributing the profile to at least one physical machine in response to a request. Software can be added to the at least one physical machine that can manage the deployment of the physical hosts as a farm to hosting the virtual images

    摘要翻译: 实施例一般涉及分发虚拟机的方法。 该方法包括基于简档中描述的要求集合,基于轻量级可重用轮廓来指定虚拟机的一组要求并实例化虚拟机。 该方法还包括将配置文件导入分发服务器; 以及响应于请求将所述简档分发到至少一个物理机器。 可以将至少一个物理机器的软件添加到可以管理物理主机作为服务器场来托管虚拟映像的至少一个物理机器上

    RFID device and method of making
    93.
    发明授权
    RFID device and method of making 有权
    RFID设备及制作方法

    公开(公告)号:US07333061B2

    公开(公告)日:2008-02-19

    申请号:US11520077

    申请日:2006-09-13

    IPC分类号: H01Q1/38

    摘要: A radio frequency identification (RFID) device includes a conductive pattern, such as an antenna, on one side of a substrate, and a chip, such as part of a strap, electrically coupled to the conductive pattern, and either on an opposite side of the substrate or on the same side of the substrate as the antenna. A method of fabricating the RFID device may include crimping the strap onto the substrate, in contact with a seed layer, which is subsequently used in forming the antenna or other conductive pattern by plating. The seed layer may be a patterned conductive ink layer. Alternatively, the seed layer may be a layer of conductive material deposited on the substrate, such as by vacuum deposition. Parts of the deposited layer may be covered with a patterned mask in order to form the desired configuration of the conductive pattern.

    摘要翻译: 射频识别(RFID)装置包括在衬底的一侧上的诸如天线的导电图案,以及电耦合到导电图案的芯片,例如带的一部分,以及与导电图案相反的一侧 衬底或与衬底相同的一侧作为天线。 制造RFID装置的方法可以包括将带绑在衬底上,与种子层接触,接种层随后用于通过电镀形成天线或其它导电图案。 种子层可以是图案化的导电油墨层。 或者,种子层可以是沉积在基底上的导电材料层,例如通过真空沉积。 沉积层的一部分可以用图案化掩模覆盖,以便形成导电图案的所需结构。

    Digital lock detector for phase-locked loop
    96.
    发明授权
    Digital lock detector for phase-locked loop 失效
    数字锁定检测器,用于锁相环

    公开(公告)号:US5909130A

    公开(公告)日:1999-06-01

    申请号:US837244

    申请日:1997-04-10

    IPC分类号: H03L7/089 H03L7/095 H03L7/08

    CPC分类号: H03L7/095 H03L7/089

    摘要: A phase lock detector circuit is disclosed that generates delayed versions of both a reference clock signal and a synthesized clock signal. From the delayed signals, first and second control signals that are pulses are generated. The pulses are passed through respective delays of predetermined durations and then clocked into respective shift registers by the latched signal of the opposite input. The shift register outputs are logically combined and shifted into a third shift register. Outputs from the third shift register are logically combined to ascertain whether a phase-lock loop is phase lock. The lock detector circuit may include a lock-out circuit to disable the phase lock detector circuit upon detecting phase lock.

    摘要翻译: 公开了一种产生参考时钟信号和合成时钟信号的延迟版本的锁相检测器电路。 从延迟信号中,产生作为脉冲的第一和第二控制信号。 脉冲通过预定持续时间的相应延迟,然后通过相对输入的锁存信号计时到相应的移位寄存器。 移位寄存器输出逻辑组合并移入第三移位寄存器。 逻辑上组合来自第三移位寄存器的输出,以确定锁相环是锁相。 锁定检测器电路可以包括锁定电路,以在检测到相位锁定时禁止锁相检测器电路。

    Low power, variable logic threshold voltage, logic gates
    97.
    发明授权
    Low power, variable logic threshold voltage, logic gates 失效
    低功耗,可变逻辑阈值电压,逻辑门

    公开(公告)号:US5847576A

    公开(公告)日:1998-12-08

    申请号:US746261

    申请日:1996-11-07

    CPC分类号: H03K19/0027 H03K19/0013

    摘要: A logic gate arrangement having a master gate or section for controlling the logic threshold voltage of slave gates responsive to the master. Both the master and slave gates have two opposite conductivity type transistors disposed in combination with a logic function circuit. The transistors have a common gate connection to a control input. Varying the voltage on the control input varies the logic threshold voltage of the gate. The logic function in the master gate is typically an inverter, with input and output connected together and driving the control inputs of the slave gates. The logic function of the slave gates may be a variety of different logic functions. The logic threshold voltage of the slave gates is substantially the same as a voltage applied to the control input of the master gate.

    摘要翻译: 具有主门或逻辑门的逻辑门装置,用于响应于主器件控制从门的逻辑阈值电压。 主门和从门均具有与逻辑功能电路组合设置的两个相反的导电型晶体管。 晶体管具有与控制输入的公共栅极连接。 改变控制输入端的电压会改变门极的逻辑门限电压。 主控门中的逻辑功能通常是一个反相器,其输入和输出连接在一起并驱动从门的控制输入。 从门的逻辑功能可能是各种不同的逻辑功能。 从门的逻辑门限电压基本上与施加到主门控制输入端的电压相同。

    Vehicle window glass antenna arrangement
    98.
    发明授权
    Vehicle window glass antenna arrangement 失效
    车窗玻璃天线布置

    公开(公告)号:US5640167A

    公开(公告)日:1997-06-17

    申请号:US379409

    申请日:1995-01-27

    申请人: Scott Wayne Hall

    发明人: Scott Wayne Hall

    IPC分类号: H01Q1/12 H01Q1/32

    CPC分类号: H01Q1/1278 H01Q1/1271

    摘要: An FM signal antenna for window glass mounting in a motor vehicle includes an elongated conductor formed as a ladder to form a series of openings along its length. Preferably, the ladder is constructed of a pair of parallel conductors and crossmember conductor segments coupled across the parallel connector. The crossmember conductors are spaced from each other a distance substantially less than the wave length of the signals to be received. In addition, the antenna includes a raised feed point positioned along the length of the conductor. The conductor has a length substantially greater than the window area so that a fold is formed in the conductor, and an extended portion of the conductor overlapping from the fold is preferably aligned with the feed point. In addition, the antenna is mounted above a heater grid comprising a plurality of transverse conductors extending between common potential conductors at either end of the grid. Preferably, equipotential line conductors extend across intermediate portions of the grid, and an equipotential line conductor is aligned with the feed point of the FM antenna.

    摘要翻译: 用于安装在机动车辆中的窗玻璃的FM信号天线包括形成为梯子的细长导体,以沿其长度形成一系列开口。 优选地,梯子由跨过并联连接器连接的一对平行导体和横梁导体段构成。 交叉构件导体彼此间隔开远小于待接收信号的波长的距离。 此外,天线包括沿着导体的长度定位的升高的馈电点。 导体的长度基本上大于窗口面积,从而在导体中形成折叠,并且导体与折叠部重叠的延伸部分优选地与馈电点对准。 此外,天线安装在加热器格栅上方,该加热器格栅包括在网格两端的公共电位导体之间延伸的多个横向导体。 优选地,等电位线导体延伸跨越电网的中间部分,并且等电位线导体与FM天线的馈电点对准。