Non-volatile memory device with conductive sidewall spacer and method for fabricating the same
    91.
    发明申请
    Non-volatile memory device with conductive sidewall spacer and method for fabricating the same 失效
    具有导电侧壁间隔物的非易失性存储器件及其制造方法

    公开(公告)号:US20060073666A1

    公开(公告)日:2006-04-06

    申请号:US11024472

    申请日:2004-12-30

    Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

    Abstract translation: 本发明涉及具有导电侧壁间隔物的非易失性存储器件及其制造方法。 非易失性存储器件包括:衬底; 形成在所述基板上的栅极绝缘层; 形成在栅极绝缘层上的栅极结构; 形成在所述栅极结构的侧壁上的一对侧壁间隔物; 一对导电侧壁间隔物,用于捕获/去除在一对侧壁间隔物上形成的电荷; 形成在所述衬底中的一对轻掺杂漏极区,所述衬底设置在所述栅极结构的侧壁下方; 以及形成在所述基板中的一对源极/漏极区域,所述基极设置在所述一对导电侧壁间隔物的边缘部分的下方。

    Method for fabricating gate-electrode of semiconductor device with use of hard mask
    93.
    发明授权
    Method for fabricating gate-electrode of semiconductor device with use of hard mask 失效
    使用硬掩模制造半导体器件栅电极的方法

    公开(公告)号:US06936529B2

    公开(公告)日:2005-08-30

    申请号:US10725320

    申请日:2003-12-02

    CPC classification number: H01L21/2807 H01L29/4941

    Abstract: The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

    Abstract translation: 本发明涉及一种制造半导体器件的栅电极的方法,所述半导体器件具有能够防止包含在栅极电极中的金属层的异常氧化并抑制应力产生的双重硬掩模。 该方法包括以下步骤:在衬底上形成栅极绝缘层; 在所述栅极绝缘层上形成至少含有金属层的栅极层结构; 在低于金属层的氧化温度的温度下在栅极层结构上形成硬掩模氧化物层; 在硬掩模氧化物层上形成硬掩模氮化物层; 将硬掩模氧化物层和硬掩模氮化物层图案化为用于形成栅电极的双重硬掩模; 以及通过使用双重硬掩模作为蚀刻掩模蚀刻栅极层结构来形成栅电极。

    Method for fabricating semiconductor device with dual gate dielectric structure
    94.
    发明申请
    Method for fabricating semiconductor device with dual gate dielectric structure 失效
    制造具有双栅电介质结构的半导体器件的方法

    公开(公告)号:US20050136593A1

    公开(公告)日:2005-06-23

    申请号:US10878346

    申请日:2004-06-29

    Abstract: Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

    Abstract translation: 公开了一种用于制造具有双栅介质结构的半导体器件的方法。 该方法包括以下步骤:在设置有用于NVDRAM的单元区域和用于逻辑电路的外围电路区域的衬底上顺序地形成第一氧化物层,氮化物层和第二氧化物层; 在细胞区域上形成掩模; 通过使用掩模作为蚀刻阻挡层去除形成在外围电路区域中的第二氧化物层来执行第一湿蚀刻工艺; 通过使用剩余在所述单元区域中的所述第二氧化物层作为蚀刻阻挡层来去除形成在所述外围电路区域中的所述氮化物层的第二湿蚀刻工艺; 在保留在外围电路区域中的第一氧化物层上形成第三氧化物层; 以及在所述第二氧化物层和所述第三氧化物层上形成栅电极。

    Method of forming dual-metal gates in semiconductor device

    公开(公告)号:US06586288B2

    公开(公告)日:2003-07-01

    申请号:US09982841

    申请日:2001-10-18

    CPC classification number: H01L21/823842 H01L29/66545

    Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.

    MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness
    97.
    发明授权
    MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness 有权
    MOSFET器件制造方法能够允许施加自对准接触工艺,同时保持金属栅极具有均匀的厚度

    公开(公告)号:US06436775B2

    公开(公告)日:2002-08-20

    申请号:US09884052

    申请日:2001-06-20

    Abstract: The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves forming a metal oxide film during the formation of a metal gate structure of the MOSFET device. The metal oxide film is formed by subjecting the gate structure through a rapid thermal oxidation (RTO) treatment and then to an N2O plasma treatment. The treatments allow the thickness of the metal oxide to be precisely controlled. The metal oxide acts as an insulator, which prevents electrical shorts between the gate structure and a contact plug even if a misalignment of occurs during the SAC process. This is an improvement from the conventional practice of separately forming a SAC barrier film after the formation of the metal gate structure and thus saves money, time, and increases reliability and productivity. Also the performance characteristics of the device is enhanced.

    Abstract translation: MOSFET制造方法允许在保持金属栅极(例如钨栅极)的同时具有均匀厚度的情况下应用自对准接触(SAC)工艺。 该过程包括在形成MOSFET器件的金属栅极结构期间形成金属氧化物膜。 金属氧化物膜通过对栅极结构进行快速热氧化(RTO)处理然后进行N 2 O等离子体处理而形成。 这些处理使金属氧化物的厚度得到精确控制。 金属氧化物充当绝缘体,即使在SAC工艺期间发生不对准,也可防止栅极结构和接触插塞之间的电短路。 这是在形成金属栅极结构之后分开形成SAC阻挡膜的常规做法的改进,从而节省了金钱,时间,并提高了可靠性和生产率。 此外,设备的性能特性也得到提高。

    Method of forming gate electrode with titanium polycide
    98.
    发明授权
    Method of forming gate electrode with titanium polycide 有权
    用多晶硅化钛形成栅电极的方法

    公开(公告)号:US06268272B1

    公开(公告)日:2001-07-31

    申请号:US09456810

    申请日:1999-12-08

    Applicant: Se Aug Jang

    Inventor: Se Aug Jang

    CPC classification number: H01L21/28247 H01L21/28061

    Abstract: A method of forming a gate electrode with a titanium polycide which can prevent particle creation and abnormal oxidation of the gate electrode, is disclosed. In the present invention, a gate oxidation process is performed after implanting Si ions into the side wall or overall surface of the titanium silicide layer, thereby preventing abnormal oxidation of the titanium silicide during the gate oxidation process. Furthermore, a titanium silicide layer is deposited to a low mole ratio of Si/Ti, thereby minimizing particle creation.

    Abstract translation: 本发明公开了一种能够防止栅电极的产生颗粒和异常氧化的多晶硅化钛形成栅电极的方法。在本发明中,在将Si离子注入侧壁或整个表面之后进行栅氧化处理 硅化钛层,从而防止了栅极氧化过程中硅化钛的异常氧化。 此外,将硅化钛层沉积成低摩尔比的Si / Ti,从而使颗粒产生最小化。

    Method for forming field oxide film of semiconductor device with silicon
and nitrogen containing etching residue
    99.
    发明授权
    Method for forming field oxide film of semiconductor device with silicon and nitrogen containing etching residue 失效
    用含氮和氮的蚀刻残渣形成半导体器件的场氧化膜的方法

    公开(公告)号:US5972779A

    公开(公告)日:1999-10-26

    申请号:US965893

    申请日:1997-11-07

    Applicant: Se Aug Jang

    Inventor: Se Aug Jang

    CPC classification number: H01L21/76202

    Abstract: A field oxide formation method involving a primary field oxidation, which is carried out at a predetermined low temperature to form a field oxide film having a thickness smaller than a target thickness, and a secondary field oxidation, which is carried out at a higher temperature capable of relatively reducing the occurrence of a field thinning phenomenon, to form the remaining thickness portion of the target field oxide film. The field thinning phenomenon involved in a field oxidation is reduced. The characteristics of a finally produced gate oxide film is also improved. Consequently, the throughput and reliability of semiconductor devices having gate oxide films are improved.

    Abstract translation: 包括初级场氧化的场氧化物形成方法,其在预定的低温下进行以形成厚度小于目标厚度的场氧化物膜和二次场氧化,其在较高的温度下进行 相对地减少场稀化现象的发生,形成目标场氧化膜的剩余厚度部分。 场氧化中涉及的场稀化现象减少。 最终生产的栅极氧化膜的特性也得到改善。 因此,提高了具有栅极氧化膜的半导体器件的吞吐量和可靠性。

    Method for forming field oxide isolation film
    100.
    发明授权
    Method for forming field oxide isolation film 失效
    形成场氧化物隔离膜的方法

    公开(公告)号:US5696022A

    公开(公告)日:1997-12-09

    申请号:US632706

    申请日:1996-04-15

    Applicant: Se Aug Jang

    Inventor: Se Aug Jang

    CPC classification number: H01L21/32 H01L21/76221

    Abstract: A method for forming a field oxide film for element isolation of a structure extending deeply in the substrate and having a step of small height, thereby exhibiting a low topology and a reduced bird's beak. The method includes the steps of forming a pattern of a mask material film for an oxidation prevention on a semiconductor substrate, locally forming an oxide film on a predetermined surface portion of the semiconductor substrate by use of an oxidation using the pattern as a mask, and removing the oxide film, thereby etching the predetermined surface portion of the semiconductor substrate while forming an undercut at a region defined beneath a side wall of the mask material film pattern, forming a lateral oxidation prevention film on the undercut disposed beneath the side wall of the mask material film pattern, and forming an oxide film for an element isolation, by use of an oxidation, on a portion of the semiconductor substrate exposed upon etching the predetermined surface portion of the semiconductor substrate.

    Abstract translation: 一种用于形成用于元件隔离的场氧化膜的方法,所述场效应晶体深度延伸到所述衬底中并且具有小高度的步骤,从而表现出低拓扑结构和减少的鸟喙。 该方法包括以下步骤:在半导体衬底上形成用于氧化防止的掩模材料膜的图案,通过使用该图案作为掩模在氧化膜上局部形成半导体衬底的预定表面部分上的氧化膜;以及 去除氧化膜,从而在掩模材料膜图案的侧壁下方限定的区域形成底切,同时蚀刻半导体衬底的预定表面部分,在设置在掩模材料膜图案的侧壁下方的底切上形成侧面防氧化膜 掩模材料膜图案,并且通过使用氧化在用于蚀刻半导体衬底的预定表面部分的暴露的半导体衬底的一部分上形成用于元件隔离的氧化膜。

Patent Agency Ranking