Touch display screen and time division driving method thereof

    公开(公告)号:US09778768B2

    公开(公告)日:2017-10-03

    申请号:US14436928

    申请日:2014-11-20

    CPC classification number: G06F3/041 G06F3/0412

    Abstract: The present invention provides a time division driving method for touch display screen, comprising multiple driving periods. For any two adjacent driving periods, in a former driving period, the method comprises: S1, providing scanning signals to N scanning lines sequentially arranged; S2, stopping providing scanning signals, and providing touch driving signals to the touch display screen; in a latter driving period, the method comprises: S3, providing scanning signals to N scanning lines sequentially arranged; S4, stopping providing scanning signals, and providing touch driving signals to the touch display screen, wherein the first n scanning lines scanned in step S3 are the last n scanning lines scanned in step S1, both N and n are positive integers and N>n; and gray-level signals of the first n scanning lines scanned in step S3 are the same as those of the last n scanning lines scanned in step S1.

    Shift Register Unit, Gate Driving Circuit And Display Apparatus
    94.
    发明申请
    Shift Register Unit, Gate Driving Circuit And Display Apparatus 有权
    移位寄存器单元,栅极驱动电路和显示装置

    公开(公告)号:US20140071104A1

    公开(公告)日:2014-03-13

    申请号:US14023728

    申请日:2013-09-11

    Abstract: A shift register unit, a gate driving circuit and a display apparatus are disclosed. The shift register unit includes a first TFT (T1) having a first electrode connected to an input terminal and a gate connected to a second clock signal input terminal; a second TFT (T2); a third TFT (T3) having a second electrode connected to an output terminal, a first electrode connected to a first clock signal input terminal, and a gate connected to the second electrode of the first TFT; a fourth TFT (T4); a fifth TFT (T5) having a gate connected to the second clock signal input terminal, a first electrode connected to the output terminal and a second electrode connected to the low potential connecting terminal; a capacitor (C1), and thus the burrs and miscellaneous spikes in a gate driving waveform outputted by the circuit can be suppressed well.

    Abstract translation: 公开了一种移位寄存器单元,栅极驱动电路和显示装置。 移位寄存器单元包括具有连接到输入端的第一电极的第一TFT(T1)和连接到第二时钟信号输入端的栅极; 第二TFT(T2); 第三TFT(T3),具有连接到输出端子的第二电极,连接到第一时钟信号输入端子的第一电极和连接到第一TFT的第二电极的栅极; 第四TFT(T4); 具有连接到第二时钟信号输入端子的栅极的第五TFT(T5),连接到输出端子的第一电极和连接到低电位连接端子的第二电极; 电容器(C1),因此可以良好地抑制由电路输出的栅极驱动波形中的毛刺和杂项尖峰。

    Display panel and display device
    97.
    发明授权

    公开(公告)号:US12243480B2

    公开(公告)日:2025-03-04

    申请号:US17997498

    申请日:2021-09-14

    Abstract: A display panel and a display device are provided. The display panel includes: a pixel unit including a pixel circuit and a light-emitting element, the pixel circuit including a driving transistor, a first reset transistor, and a second reset transistor; a first initialization signal line, connected to a first electrode of the first reset transistor; a first reset control signal line, connected to a gate electrode of the first reset transistor; and a second initialization signal line, connected to a first electrode of the second reset transistor, the first initialization signal line and the second initialization signal line are located in a same layer, and are located in a different layer from the first reset control signal line, the first reset control signal line is located between the first initialization signal line the second initialization signal line.

    Pixel driving circuit and driving method thereof, and display panel

    公开(公告)号:US12205542B2

    公开(公告)日:2025-01-21

    申请号:US18014766

    申请日:2021-07-30

    Abstract: A pixel driving circuit includes: a driving transistor, a data write circuit, a threshold compensation circuit, a first capacitor, and a second capacitor. A gate of the driving transistor is coupled to a first node, a first electrode is coupled to a second node, and a second electrode is coupled to a third node. The data write circuit is configured to transmit a signal of a data signal terminal to the second node in response to a signal of a first gate driving signal terminal. The threshold compensation circuit is configured to communicate the first node with the third node in response to a signal of a second gate driving signal terminal. The first capacitor is coupled between the first node and the first gate driving signal terminal. The second capacitor is coupled between the first node and the second gate driving signal terminal.

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