公开(公告)号：US20220294948A1

公开(公告)日：2022-09-15

申请号：US17197784

申请日：2021-03-10

Applicant: Google LLC

Inventor： Sangmoo Choi ,  Lu Gao ,  Yoshimichi Matsuoka

IPC: H04N5/225 ,  H04N5/238 ,  G09G3/3208

Abstract: A computing device includes a display panel having a first end and a second end, a sensor, and a processing circuitry. The display panel includes a matrix of pixels and defines an aperture surrounded by pixels of the matrix of pixels but that does not include pixels of the matrix of pixels. A length of the aperture parallel to an axis connecting the first end and the second end is greater than a length of the aperture perpendicular to the axis. The sensor is configured to capture light that passes through the aperture. The processing circuitry, disposed proximal to the second end, is configured to output control signals to pixels of the matrix of pixels.

公开(公告)号：US20220270550A1

公开(公告)日：2022-08-25

申请号：US17662972

申请日：2022-05-11

Applicant: Google LLC

Inventor： Sangmoo Choi ,  Chang Ju Kang

IPC: G09G3/3258

Abstract: This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.

公开(公告)号：US20220020323A1

公开(公告)日：2022-01-20

申请号：US17311632

申请日：2019-08-01

Applicant: GOOGLE LLC

Inventor： Sangmoo Choi ,  Wonjae Choi ,  Sang Young Youn ,  Sun-il Chang

IPC: G09G3/3225 ,  G09G3/20

Abstract: A method for driving an organic light emitting diode display having a first plurality of pixel lines having a first pixel density and a second plurality of pixel lines having a second pixel density higher than the first pixel density, the method including driving the first and second plurality of pixel lines with corresponding drive signals at a frame rate at which frames are displayed, where during each of the frames the drive signals have a pixel on time during which pixels in the pixel lines driven by the drive signals emit light and a pixel off time during which pixels in the pixel lines driven by the drive signals are dark, where the pixel on times and the pixel off times are varied between the drive signals to reduce variations in luminance.

公开(公告)号：US20210366398A1

公开(公告)日：2021-11-25

申请号：US17394953

申请日：2021-08-05

Applicant: Google LLC

Inventor： Sangmoo Choi

IPC: G09G3/3258 ,  G09G3/3291

Abstract: This document describes systems and techniques for delaying anode voltage reset for quicker response times in organic light-emitting diode (OLED) displays. In an aspect, a pixel circuit includes a transistor electrically connected to an anode of an organic light-emitting diode and a reset voltage. Upon receiving an anode reset signal, the transistor completes the circuit causing the anode voltage to reset to the reset voltage in an anode voltage reset process. Delaying anode voltage reset can hasten response times in OLED displays.

公开(公告)号：US20200320923A1

公开(公告)日：2020-10-08

申请号：US16372865

申请日：2019-04-02

Applicant: Google LLC

Inventor： Sangmoo Choi ,  Chang Ju Kang

IPC: G09G3/20

Abstract: A flat panel display that includes a switch bank to couple a signal from a driver integrated circuit to a column data line of a display panel is disclosed. The switch bank can be adjusted based on the frame rate of the display. When the frame rate is high, all sub-switches in the switch bank may be used to reduce an ON resistance of the switch bank. This high frame rate configuration may maintain or increase the speed at which pixels can be controlled but consumes more power. Accordingly, when the frame rate is low, a portion of the sub-switches in the switch bank are unused to reduce the power consumed. This low frame rate configuration may maintain or decrease the speed at which pixels of the display can be controlled but consumes less power.