公开(公告)号：US07175943B2

公开(公告)日：2007-02-13

申请号：US10725571

申请日：2003-12-03

申请人： Masafumi Asano ,  Tadahito Fujisawa ,  Satoshi Tanaka

发明人： Masafumi Asano ,  Tadahito Fujisawa ,  Satoshi Tanaka

IPC分类号： G01F9/00

CPC分类号： G03F7/70466 ,  G03F1/44 ,  G03F1/70 ,  G03F7/70625

摘要： A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.

公开(公告)号：US20070033083A1

公开(公告)日：2007-02-08

申请号：US11497272

申请日：2006-08-02

申请人： Kenji Sakamoto ,  Naoharu Yamada ,  Goro Kunito ,  Satoshi Tanaka ,  Kenichi Yamazaki

发明人： Kenji Sakamoto ,  Naoharu Yamada ,  Goro Kunito ,  Satoshi Tanaka ,  Kenichi Yamazaki

IPC分类号： G06F9/44 ,  G06F17/50

CPC分类号： G06F3/002 ,  G06F17/2785 ,  G06Q10/063 ,  G06Q30/0201

摘要： A noun and a verb is mapped as the information about an article to which an article identifier such as a radio tag, etc. is attached and a user activity, thereby estimating a user activity from the article to which the article identifier is attached and providing a user with appropriate information. An article identifier for identification of an article is associated with article information and stored (step S202), and the relationship between a noun relating to the article information and a verb relating to the article are associated with a conditional probability and held in the probability information holding unit (step S207). Upon detection of the article identifier, the probability of the verb to the noun is calculated based on the contents held in the probability information holding unit, thereby estimating a user activity (step S212). Thus, based on the detection result of the article identifier attached to the article, the activity of the user on the article can be estimated. As a result, an appropriate service can be provided for the activity of the user.

摘要翻译： 名词和动词被映射为关于诸如无线电标签等的文章标识符附加的文章的信息和用户活动，从而从文章标识符附加的文章估计用户活动并提供 具有适当信息的用户。 用于标识物品的物品标识符与物品信息相关联并存储（步骤S 202），并且与物品信息有关的名词与与物品相关的动词之间的关系与条件概率相关联并且以概率保持 信息保存单元（步骤S207）。 在检测到物品标识符时，基于保持在概率信息保持单元中的内容来计算动词到名词的概率，由此估计用户活动（步骤S 212）。 因此，基于附于物品的物品识别符的检测结果，可以估计用户对物品的活动。 因此，可以为用户的活动提供适当的服务。

公开(公告)号：US20070006115A1

公开(公告)日：2007-01-04

申请号：US11472441

申请日：2006-06-22

申请人： Shigeki Nojima ,  Yoko Oikawa ,  Satoshi Tanaka

发明人： Shigeki Nojima ,  Yoko Oikawa ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is prepared. Mask pattern data on a pattern of a mask used in order to produce the design circuit pattern is prepared. A circuit pattern which is to be obtained by processing a film using the pattern of the mask indicated by the mask pattern data is acquired. Circuit data on a circuit realized by at least a first part of the circuit pattern is produced. A circuit mismatch part where the circuit data and a part of the design circuit data which corresponds to the first part of the circuit pattern do not match up is detected.

摘要翻译： 一种验证掩模图案数据的方法包括：在设计电路上准备设计电路数据，实现所需的电气操作。 制备具有实现半导体衬底上的设计电路的结构的设计电路图案的数据。 准备用于产生设计电路图案的掩模图形上的掩模图案数据。 获取通过使用由掩模图案数据指示的掩模的图案来处理胶片而获得的电路图案。 产生由电路图案的至少第一部分实现的电路上的电路数据。 检测与电路图案的第一部分对应的电路数据和设计电路数据的一部分不匹配的电路失配部。

公开(公告)号：US07120882B2

公开(公告)日：2006-10-10

申请号：US11105431

申请日：2005-04-14

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

公开(公告)号：US07116709B2

公开(公告)日：2006-10-03

申请号：US10860324

申请日：2004-06-04

申请人： Satoshi Tanaka ,  Tomoaki Ishifuji ,  Kenji Nagai ,  Katsuhiro Furukawa

发明人： Satoshi Tanaka ,  Tomoaki Ishifuji ,  Kenji Nagai ,  Katsuhiro Furukawa

IPC分类号： H03K7/04

CPC分类号： G06K7/0008 ,  H04L25/4904

摘要： The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and “1” and “0” are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed.

摘要翻译： 代码系统是通过以下方式实现的：每个具有占空比为50％的多个波形A和B，其中仅存在上升沿和下降沿中的任何一个，“1”和“0” 被分配给组合波形。 根据本发明，可以同时发送时钟和数据，并且可以容易地解调而不使用复合PLL电路。 作为根据本发明的试制，可以实现解调器，其可以在2V的工作电压下允许输入频率中包含的变化大于1位。可以确认该专利的有效性。

公开(公告)号：US07103337B2

公开(公告)日：2006-09-05

申请号：US10373020

申请日：2003-02-26

申请人： Toshiya Uozumi ,  Satoshi Tanaka ,  Masumi Kasahara ,  Hirotaka Oosawa ,  Yasuyuki Kimura ,  Robert Astle Henshaw

发明人： Toshiya Uozumi ,  Satoshi Tanaka ,  Masumi Kasahara ,  Hirotaka Oosawa ,  Yasuyuki Kimura ,  Robert Astle Henshaw

IPC分类号： H04B1/06

CPC分类号： H03L7/0898 ,  H03F1/0211 ,  H03F1/0266 ,  H03F1/0272 ,  H03F1/345 ,  H03F2200/294 ,  H03F2200/372 ,  H03G3/3042 ,  H03G3/3047 ,  H03L7/099 ,  H03L7/187 ,  H04B2001/0416 ,  H04L27/0008 ,  H04L27/2017 ,  H04L27/2071 ,  H04L27/361 ,  H04L27/368

摘要： A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

摘要翻译： 用于通信的半导体集成电路器件设置有形成在其中的PLL电路等，PLL电路能够实现由于温度变化引起的波动的补偿，芯片面积的增加的抑制以及性能的确定 边缘，并且其控制具有多个振荡频带的VCO。 在通过使用具有多个振荡频带的VCO将开关切换到PLL电路中的直流电压源的一侧进行自动校准的情况下，将RFVCO的调谐电压（Vtune）固定为DC的电压值 电压源。 然而，由于将VCO振荡频率的温度特性赋予DC电压源，所以当校准表达到最佳时，可以最小化对频带选择的影响。

公开(公告)号：US07090949B2

公开(公告)日：2006-08-15

申请号：US10724738

申请日：2003-12-02

申请人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

发明人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

IPC分类号： G01F9/00

CPC分类号： G03F1/36 ,  G03F1/68

摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.

摘要翻译： 公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应 对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取 基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸 预定条件。

公开(公告)号：US20060127690A1

公开(公告)日：2006-06-15

申请号：US10541904

申请日：2004-01-16

申请人： Ryuji Ueda ,  Satoshi Tanaka ,  Osamu Koga ,  Fusao Takagi ,  Hiroshi Matsuzawa ,  Yusuke Onoda ,  Shingo Akao

发明人： Ryuji Ueda ,  Satoshi Tanaka ,  Osamu Koga ,  Fusao Takagi ,  Hiroshi Matsuzawa ,  Yusuke Onoda ,  Shingo Akao

IPC分类号： C23F1/00 ,  C25D1/08 ,  B21D31/04

CPC分类号： C23F1/02 ,  H01L23/49548 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/064 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T428/12361 ,  Y10T428/12368 ,  Y10T428/24273 ,  H01L2924/00

摘要： A metal photoetching product comprising at least one large cavity of minor axis W1S, major axis W1L and depth D1 in a surface of the product, wherein one or more cavities are included inside at least one of the at least one large cavity, and a smallest hole among the cavities has minor axis of W2S, major axis W2L, and depth D2; and the product satisfies the following dimensions, D1+D2=plate thickness D, 0.02 mm≦D≦2 mm, 0.4×D

摘要翻译： 一种金属光刻产品，其包括产品表面中的至少一个小轴W 1 S，长轴W 1 L L和深度D 1的大空腔，其中一个或 在所述至少一个大空腔中的至少一个中包括更多的空腔，并且所述空腔中的最小孔具有W 2 S的短轴，长轴W 2 L ，深度D 2; 并且该产品满足以下尺寸：D 1 + D 2 =板厚度D，0.02mm <= D <= 2mm，0.4×D D和0.2×D 2