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公开(公告)号:US20180114846A1
公开(公告)日:2018-04-26
申请号:US15333262
申请日:2016-10-25
IPC分类号: H01L29/66 , H01L29/78 , H01L23/535 , H01L29/06 , H01L21/768 , H01L29/417
CPC分类号: H01L29/665 , H01L21/76895 , H01L23/535 , H01L29/0649 , H01L29/41791 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785
摘要: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
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公开(公告)号:US20180108752A1
公开(公告)日:2018-04-19
申请号:US15835906
申请日:2017-12-08
发明人: Sivananda K. Kanakasabapathy , Gauri Karve , Juntao Li , Fee Li Lie , Stuart A. Sieg , John R. Sporre
CPC分类号: H01L29/6681 , H01L21/3086 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/0657 , H01L29/42356 , H01L29/66795 , H01L29/7842 , H01L29/7845 , H01L29/7846 , H01L29/785
摘要: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.
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公开(公告)号:US20180090606A1
公开(公告)日:2018-03-29
申请号:US15629280
申请日:2017-06-21
发明人: Huiming Bu , Kangguo Cheng , Dechao Guo , Sivananda K. Kanakasabapathy , Peng Xu
IPC分类号: H01L29/78 , H01L29/06 , H01L29/66 , H01L21/324 , H01L21/3065
摘要: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
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公开(公告)号:US20180090599A1
公开(公告)日:2018-03-29
申请号:US15652888
申请日:2017-07-18
发明人: Huiming Bu , Kangguo Cheng , Dechao Guo , Sivananda K. Kanakasabapathy , Peng Xu
CPC分类号: H01L29/785 , H01L21/3065 , H01L21/324 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L29/0649 , H01L29/0653 , H01L29/1037 , H01L29/16 , H01L29/161 , H01L29/66795 , H01L29/66818 , H01L29/7851
摘要: Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.
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公开(公告)号:US20180090385A1
公开(公告)日:2018-03-29
申请号:US15718577
申请日:2017-09-28
发明人: Zhenxing Bi , Donald F. Canaperi , Thamarai S. Devarajan , Sivananda K. Kanakasabapathy , Fee Li Lie , Peng Xu
IPC分类号: H01L21/8234 , H01L21/311 , H01L21/762
CPC分类号: H01L21/823481 , H01L21/0206 , H01L21/31111 , H01L21/31116 , H01L21/31138 , H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L29/0649 , H01L29/0653 , H01L29/66795 , H01L29/7851
摘要: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
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公开(公告)号:US20180083117A1
公开(公告)日:2018-03-22
申请号:US15826346
申请日:2017-11-29
发明人: Takashi Ando , Johnathan E. Faltermeier , Su Chen Fan , Sivananda K. Kanakasabapathy , Injo Ok , Tenko Yamashita
IPC分类号: H01L29/49 , H01L21/8234 , H01L29/423 , H01L27/088 , H01L29/40 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号: H01L29/4966 , H01L21/28088 , H01L21/823431 , H01L21/823456 , H01L21/845 , H01L27/088 , H01L29/401 , H01L29/42376 , H01L29/517 , H01L29/66545 , H01L29/66795
摘要: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.
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公开(公告)号:US20180061942A1
公开(公告)日:2018-03-01
申请号:US15794636
申请日:2017-10-26
发明人: Bruce B. Doris , Hong He , Sivananda K. Kanakasabapathy , Gauri Karve , Fee Li Lie , Derrick Liu , Soon-Cheon Seo , Stuart A. Sieg
CPC分类号: H01L29/0649 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
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公开(公告)号:US20180061941A1
公开(公告)日:2018-03-01
申请号:US15794616
申请日:2017-10-26
发明人: Bruce B. Doris , Hong He , Sivananda K. Kanakasabapathy , Gauri Karve , Fee Li Lie , Derrick Liu , Soon-Cheon Seo , Stuart A. Sieg
CPC分类号: H01L29/0649 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
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公开(公告)号:US20180006150A1
公开(公告)日:2018-01-04
申请号:US15197996
申请日:2016-06-30
发明人: Brent A. Anderson , Sivananda K. Kanakasabapathy , Jeffrey C. Shearer , Stuart A. Sieg , John R. Sporre , Junli Wang
IPC分类号: H01L29/78 , H01L29/49 , H01L21/3065 , H01L21/033 , H01L29/66 , H01L21/02
CPC分类号: H01L29/7827 , H01L29/66666 , H01L29/66795 , H01L29/785
摘要: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
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公开(公告)号:US09859224B2
公开(公告)日:2018-01-02
申请号:US15239166
申请日:2016-08-17
发明人: David J. Conklin , Allen H. Gabor , Sivananda K. Kanakasabapathy , Byeong Y. Kim , Fee Li Lie , Stuart A. Sieg
IPC分类号: H01L21/311 , H01L23/544 , H01L21/308 , G03F7/20 , H01L21/033 , G03F9/00
CPC分类号: H01L23/544 , G03F7/70633 , G03F7/70683 , G03F9/708 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/31111 , H01L21/31144 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453
摘要: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.
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