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    ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
    91.
    发明申请
    ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT 有权
    通过电路互连连接

    公开(公告)号：US20100164116A1

    公开(公告)日：2010-07-01

    申请号：US12344838

    申请日：2008-12-29

    申请人： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

    发明人： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

    IPC分类号： H01L23/52 ,  H01L21/4763 ,  H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

    摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。

    Trench type buried on-chip precision programmable resistor
    93.
    发明授权
    Trench type buried on-chip precision programmable resistor 有权
    沟槽型嵌入式片上精密可编程电阻器

    公开(公告)号：US07601602B2

    公开(公告)日：2009-10-13

    申请号：US11481514

    申请日：2006-07-06

    申请人： John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

    发明人： John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

    IPC分类号： H01L21/04

    CPC分类号： H01L28/20 ,  H01L27/101

    摘要： An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

    摘要翻译： 一种片上超小型可编程半导体电阻器件及器件结构及其制造方法。 每个半导体电阻器件结构由表现出精确电阻值的一个或多个导电连接的埋沟槽型电阻器元件形成。 至少两个半导体电阻器件结构可以通过一个或多个保险丝器件的中间串联或并联配置连接，该熔丝器件可以被吹制以实现期望的总电阻值。

    STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY
    95.
    发明申请
    STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY 有权
    半导体芯片修复方案结构的负偏差温度不稳定性

    公开(公告)号：US20090183131A1

    公开(公告)日：2009-07-16

    申请号：US12050990

    申请日：2008-03-19

    申请人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    发明人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    IPC分类号： G06F17/50

    CPC分类号： H01L23/345 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

    摘要翻译： 公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

    Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof
    98.
    发明授权
    Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
    集成电路制造期间电荷耗散的方法和结构及其分离

    公开(公告)号：US07445966B2

    公开(公告)日：2008-11-04

    申请号：US11160468

    申请日：2005-06-24

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

    IPC分类号： H01L23/60

    CPC分类号： H01L27/0248 ,  Y10S438/926

    摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

    摘要翻译： 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

    Heat dissipation from IC interconnects
    100.
    发明授权
    Heat dissipation from IC interconnects 失效
    IC互连散热

    公开(公告)号：US06798066B1

    公开(公告)日：2004-09-28

    申请号：US10249910

    申请日：2003-05-16

    申请人： William T. Motsiff ,  Timothy D. Sullivan ,  Jean E. Wynne ,  Sally J. Yankee

    发明人： William T. Motsiff ,  Timothy D. Sullivan ,  Jean E. Wynne ,  Sally J. Yankee

    IPC分类号： H01L2348

    CPC分类号： H01L23/60 ,  H01L23/36 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to dissipating heat from an interconnect formed in a low thermal conductivity dielectric in an integrated circuit apparatus. The integrated circuit apparatus includes integrated circuit devices interconnected by conductive interconnection metallurgy and input/output pads subject to electrostatic discharge events. At least one latent heat of transformation absorber is associated with at least one of the input/output pads for preventing the energy generated by an electrostatic discharge event from damaging the conductive interconnection metallurgy.

    摘要翻译： 本发明涉及从形成在集成电路装置中的低导热电介质中的互连件散热。 集成电路装置包括通过导电互连冶金互连的集成电路装置和经受静电放电事件的输入/输出垫。 至少一个变换吸收器的潜热与至少一个输入/输出焊盘相关联，用于防止由静电放电事件产生的能量损坏导电互连冶金。