公开(公告)号：US07521760B2

公开(公告)日：2009-04-21

申请号：US11775607

申请日：2007-07-10

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00 ,  H01L47/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US20080298520A1

公开(公告)日：2008-12-04

申请号：US12218272

申请日：2008-07-14

申请人： Louis C. Hsu ,  Brian L. Ji ,  James S. Mason ,  Karl D. Selander ,  Michael A. Soma ,  Steven J. Zier

发明人： Louis C. Hsu ,  Brian L. Ji ,  James S. Mason ,  Karl D. Selander ,  Michael A. Soma ,  Steven J. Zier

IPC分类号： H04L27/08

CPC分类号： H04L25/085 ,  H03F1/3241 ,  H04L25/0278 ,  H04L25/0292 ,  H04L25/03343 ,  H04L25/061 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03808

摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.

摘要翻译： 提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。 接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

公开(公告)号：US20080289651A1

公开(公告)日：2008-11-27

申请号：US11753711

申请日：2007-05-25

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman

IPC分类号： B08B6/00

CPC分类号： B08B7/0042 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/67086

摘要： A wafer edge cleaning system that includes a wafer dry etching chamber and one or more irradiation sources preferably positioned inside the wafer dry etching chamber. The irradiation source such as laser generates a beam aimed at the periphery of the wafer to melt any defects, in particular, black silicon at the edge of the wafer. Preferably, the wafer is mounted on a rotating platform. The invention further provides a method for removing black silicon at the edge of a semiconductor wafer that includes the steps of: patterning the wafer with a trench mask layer; etching the wafer to form a trench thereon; exposing the edge of the wafer to a laser beam to melt the black silicon thereon; stripping the mask and cleaning the wafer.

摘要翻译： 一种晶片边缘清洁系统，其包括晶片干蚀刻室和优选位于晶片干蚀刻室内部的一个或多个照射源。 诸如激光器的照射源产生瞄准晶片周边的光束，以熔化晶片边缘的任何缺陷，特别是黑色硅。 优选地，晶片安装在旋转平台上。 本发明还提供一种在半导体晶片的边缘处去除黑硅的方法，包括以下步骤：用沟槽掩模层图案化晶片; 蚀刻晶片以在其上形成沟槽; 将晶片的边缘暴露于激光束以在其上熔化黑色硅; 剥去掩模并清洁晶片。

公开(公告)号：US20080220280A1

公开(公告)日：2008-09-11

申请号：US11682403

申请日：2007-03-06

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

IPC分类号： B05D5/12 ,  H01L29/12

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

公开(公告)号：US20080186085A1

公开(公告)日：2008-08-07

申请号：US12060893

申请日：2008-04-02

申请人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

发明人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

IPC分类号： G05F3/16

CPC分类号： H03H11/24

摘要： A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

公开(公告)号：US07394332B2

公开(公告)日：2008-07-01

申请号：US11217163

申请日：2005-09-01

申请人： Louis C. Hsu ,  Lowrence A. Clevenger ,  Timothy J. Dalton ,  Carl J. Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Lowrence A. Clevenger ,  Timothy J. Dalton ,  Carl J. Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01P1/10

CPC分类号： H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

摘要： A MEM switch is described having a free moving element within in micro-cavity, and guided by at least one inductive element. The switch consists of an upper inductive coil; an optional lower inductive coil, each having a metallic core preferably made of permalloy; a micro-cavity; and a free-moving switching element preferably also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When the chip is not mounted with the correct orientation, gravity cannot be used. In such an instance, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

摘要翻译： 描述了一种MEM开关，其具有在微腔内的自由移动元件，并由至少一个电感元件引导。 开关由上感应线圈组成; 可选的下感应线圈，每个具有优选由坡莫合金制成的金属芯; 微腔; 以及优选也由磁性材料制成的自由移动的开关元件。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，短路两根开放的电线，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当芯片未正确安装时，重力不能使用。 在这种情况下，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：US07298639B2

公开(公告)日：2007-11-20

申请号：US10908245

申请日：2005-05-04

申请人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： G11C17/00

CPC分类号： H01L23/5256 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 使用电迁移效应对可电熔熔丝进行编程，并使用反向电迁移效应进行重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US07232745B2

公开(公告)日：2007-06-19

申请号：US11064730

申请日：2005-02-24

申请人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv Vasant Joshi

发明人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv Vasant Joshi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

公开(公告)号：US07205816B2

公开(公告)日：2007-04-17

申请号：US11155848

申请日：2005-06-17

申请人： Herschel A. Ainspan ,  Gautam Gangasani ,  Louis C. Hsu ,  Jack A. Mandelman

发明人： Herschel A. Ainspan ,  Gautam Gangasani ,  Louis C. Hsu ,  Jack A. Mandelman

IPC分类号： H03K3/00 ,  G06G7/12

CPC分类号： G06F1/04

摘要： An apparatus and method for generating high-speed clock signals using a voltage-controlled-oscillator (VCO) device. The apparatus implements a linear variable gain amplifier rather than a non-linear hard limiter to remove unwanted signal modulation in VCO output signals. Implementation of the linear variable gain amplifier leads to the generation of amplitude modulation-free oscillation leading to the generation of jitter free high frequency clock signals.

摘要翻译： 一种使用压控振荡器（VCO）装置产生高速时钟信号的装置和方法。 该装置实现线性可变增益放大器，而不是非线性硬限幅器，以消除VCO输出信号中不需要的信号调制。 线性可变增益放大器的实现导致无振幅调制的产生，导致产生无抖动的高频时钟信号。

公开(公告)号：US07078320B2

公开(公告)日：2006-07-18

申请号：US10710880

申请日：2004-08-10

申请人： Louis C. Hsu ,  Hsichang Liu ,  James R. Salimeno, III

发明人： Louis C. Hsu ,  Hsichang Liu ,  James R. Salimeno, III

IPC分类号： H01L21/326 ,  H01L21/46

CPC分类号： H01L21/2007 ,  H01L21/78 ,  Y10S438/977

摘要： Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.

摘要翻译： 公开了一种制造在有限数量的接合点部分地将集成电路晶片连接到支撑晶片的集成电路芯片的方法。 一旦接合，集成电路晶片被化学机械抛光以减小集成电路晶片的厚度。 然后，在减小集成电路晶片的厚度之后，本发明对集成电路晶片进行常规处理，以在集成电路晶片中形成器件和布线。 接下来，本发明切割集成电路晶片和支撑晶片以形成芯片部分。 在该切割过程中，集成电路晶片与集成电路晶片通过接合点未接合到支撑晶片的芯片部分中的支撑晶片分离。 集成电路晶片保持接合到支撑晶片的芯片部分比集成电路晶片与支撑晶片分离的芯片部分更厚。