公开(公告)号：US20050083950A1

公开(公告)日：2005-04-21

申请号：US10868479

申请日：2004-06-14

申请人： Su Choi ,  Tae Kim ,  Hyeong Lee

发明人： Su Choi ,  Tae Kim ,  Hyeong Lee

IPC分类号： H04L12/28 ,  H04L1/00 ,  H04Q11/00

CPC分类号： H04Q11/0067 ,  H04Q11/0066 ,  H04Q11/0071 ,  H04Q2011/0077

摘要： Disclosed herein is a shared Local Area Network (LAN) emulation method and apparatus. The method includes the following four steps. At the first step, a Logical Link Identifier (LLID) management table is set up to assign unique LLIDs to a plurality of Optical Network Units (ONUs) and manage the assigned LLIDs so as to identify the plurality of ONUs connected to a single Optical Line Terminal (OLT). Thereafter, a MAC address table is set up for the LLIDs to learn MAC addresses of the ONUs. Thereafter, the unique LLIDs are assigned to ONUs when the ONUs request registration from the OLT. Finally, data frames, which are received by a Shared LAN Emulation (SLE) layer of the OLT, are bridged using the LLIDs, VIDs of Virtual LANs to which the ONUs belong and destination MAC addresses of the data frames so as to provide a single matched port between a Logical Link Control (LLC) layer and a MAC layer of the OLT.

摘要翻译： 这里公开了共享的局域网（LAN）仿真方法和装置。 该方法包括以下四个步骤。 在第一步，建立逻辑链路标识符（LLID）管理表以将多个光网络单元（ONU）分配唯一的LLID并管理所分配的LLID，以便识别连接到单个光线路的多个ONU 终端（OLT）。 此后，为LLID建立MAC地址表，以学习ONU的MAC地址。 此后，当ONU从OLT请求注册时，将唯一的LLID分配给ONU。 最后，由OLT的共享LAN仿真（SLE）层接收的数据帧使用LLID，ONU所属的虚拟LAN的VID和数据帧的目标MAC地址进行桥接，以提供单个 逻辑链路控制（LLC）层和OLT的MAC层之间的匹配端口。

公开(公告)号：US08644091B2

公开(公告)日：2014-02-04

申请号：US13595857

申请日：2012-08-27

申请人： Tae Kim

发明人： Tae Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

摘要： A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20130069328A1

公开(公告)日：2013-03-21

申请号：US13420491

申请日：2012-03-14

申请人： Randal Hetrick ,  Tae Kim ,  Christine Marcelino ,  Stephanie Russo

发明人： Randal Hetrick ,  Tae Kim ,  Christine Marcelino ,  Stephanie Russo

IPC分类号： B60B33/00 ,  B62B3/00

CPC分类号： B60B33/0005 ,  A63B7/00 ,  A63B71/00 ,  A63B2071/025 ,  B62B3/00

摘要： A caster assembly for a frame is described that permits a frame to be easily moved and placed. The caster assembly, which may lift a leg of the frame, can be placed or removed without picking up the frame. The caster assembly further includes a handle that moves a cam for engaging the caster assembly with the leg. A frame having at least one caster assembly is also described.

摘要翻译： 描述了一种用于框架的脚轮组件，其允许框架容易地移动和放置。 脚轮组件可以提起框架的腿部，可以放置或移除，而不必拿起框架。 脚轮组件还包括手柄，该手柄使用于与脚轮接合的脚轮组件的凸轮移动。 还描述了具有至少一个脚轮组件的框架。

公开(公告)号：US20110032002A1

公开(公告)日：2011-02-10

申请号：US12906806

申请日：2010-10-18

申请人： Tae Kim ,  Howard C. Kirsch

发明人： Tae Kim ,  Howard C. Kirsch

IPC分类号： G01R19/00

CPC分类号： G11C7/08 ,  G11C7/062

摘要： Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.

摘要翻译： 针对电压补偿的读出放大器描述实施例。 一个这样的感测放大器包括分别耦合到一对晶体管的一对数字线节点。 第一对开关适于将晶体管的栅极交叉耦合到相应的数字线节点，并且第二对开关适于将晶体管的栅极耦合到电压源。 第一和第二对开关耦合到晶体管的相应栅极，独立于一对晶体管分别耦合到数字线节点。

公开(公告)号：US20100019804A1

公开(公告)日：2010-01-28

申请号：US12573750

申请日：2009-10-05

申请人： Chulmin Jung ,  Tae Kim

发明人： Chulmin Jung ,  Tae Kim

IPC分类号： H03F3/45

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

摘要翻译： 描述了具有减小的增益的放大器级的读出放大器。 读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。 读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。 具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。 具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。 读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。

公开(公告)号：US20090168551A1

公开(公告)日：2009-07-02

申请号：US12399757

申请日：2009-03-06

申请人： Tae Kim ,  Charles L. Ingalls ,  David Pinney ,  Howard Kirsch

发明人： Tae Kim ,  Charles L. Ingalls ,  David Pinney ,  Howard Kirsch

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C5/14

CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/2227

摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.

摘要翻译： 感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。 在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。 响应于驱动电压而锁存数据状态。 在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内从读出放大器去耦。 数字线以跟随第二时间段的受控速率耦合到读出放大器。

公开(公告)号：US07535282B2

公开(公告)日：2009-05-19

申请号：US11146852

申请日：2005-06-07

申请人： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  David Pinney

发明人： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  David Pinney

IPC分类号： H03K19/017 ,  G05F1/575 ,  H01L27/04

CPC分类号： G05F3/205 ,  H03K17/302

摘要： The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.

摘要翻译： 动态地调整DRAM读出放大器电路中的NCH晶体管的p阱背偏置。 优选地，在感测期间，感测放大器的NCH晶体管的p阱反向偏置被增加以实际上降低NCH晶体管的阈值电压，使得它们在感测期间更容易被激活。 背偏置电压优选地从地（其正常值）增加到NCH晶体管（NVt）的阈值电压，其值足够低以防止电路闭锁。 此外，该电压优选地使用接收p阱偏置电压作为反馈的Vt检测器/偏置电路来实现。 在使公开的感测放大器电路受益的同时，提供给NCH晶体管的p阱的动态偏置也可以有益于其它CMOS电路中的NCH晶体管。 此外，还提供了对CMOS电路中的PCH晶体管的n阱动态偏置的类似修改，以增加PCH晶体管的感测裕度。

公开(公告)号：US07505341B2

公开(公告)日：2009-03-17

申请号：US11436863

申请日：2006-05-17

申请人： Tae Kim ,  Charles L. Ingalls ,  David Pinney ,  Howard Kirsch

发明人： Tae Kim ,  Charles L. Ingalls ,  David Pinney ,  Howard Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/2227

摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.

公开(公告)号：US07372746B2

公开(公告)日：2008-05-13

申请号：US11205659

申请日：2005-08-17

申请人： Tae Kim

发明人： Tae Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

摘要： A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes.

摘要翻译： 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在存储器的有功断电状态期间，由于使用具有低阈值电压（Vth）的P和Nsense放大器用于数据信号的低Vcc感测，漏电流可能增加。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。

公开(公告)号：US20080095211A1

公开(公告)日：2008-04-24

申请号：US11577212

申请日：2005-12-14

申请人： Jong Jun You ,  Young Kim ,  Tae Kim

发明人： Jong Jun You ,  Young Kim ,  Tae Kim

IPC分类号： G01N25/00

CPC分类号： G01R31/2865 ,  G01R31/2868 ,  G01R31/2877 ,  G01R31/2887

摘要： Provided is a apparatus for testing reliability of a semiconductor sample including: a sample mounting part for mounting the semiconductor sample on an upper center part thereof, and mounting components having an evaluation circuit board at an upper peripheral part thereof; a heating block formed to have a tip shape and mounted on a lower part of the semiconductor sample to maintain a test temperature; a cooling block separated from the heating block and surrounding the heating block to cool the temperature of the components; and a fixing block for raising and lowering the semiconductor sample.

摘要翻译： 提供了一种用于测试半导体样品的可靠性的装置，包括：用于将半导体样品安装在其上部中心的样品安装部分和在其上部周边具有评估电路板的安装部件; 加热块形成为具有尖端形状并且安装在半导体样品的下部以保持测试温度; 冷却块与加热块分离并围绕加热块以冷却部件的温度; 以及用于升高和降低半导体样品的固定块。