摘要:
A driver chain circuit and methods are provided. The driver chain circuit includes a plurality of voltage regulators and an inverter chain. The plurality of voltage regulators are operable to provide a bias to respective groups of one or more inverters within the inverter chain. The inverter chain includes a plurality of groups of one or more inverters. Each group of inverters is configured to receive a bias from a respective one of the plurality of voltage regulators.
摘要:
A system includes a first filter generating a first output signal based on an input signal. The first filter includes N tap weight coefficients, where N is an integer greater than 1. A first device updates the N tap weight coefficients of the first filter. A second filter generates a second output signal in response to the first output signal. The second filter includes M tap weight coefficients, where M is an integer greater than 1 and less than N. A second device determines a value of a first one of the M tap weight coefficients for each of multiple sampling times of the input signal. The second device updates the first one of the M tap weight coefficients based on the values of the first one of the M tap weight coefficients, a first gain constant, and a change in timing phase error of the first filter.
摘要:
A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor.
摘要:
Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
摘要:
A storage system includes a first buffer configured to store a first repeatable runout profile (RRP) for a sector of a rotating storage medium. A second buffer is configured to store a second RRP for the sector. A controller: controls a servo of the rotating storage medium based on the first RRP during a first revolution of the rotating storage medium; and learns the second RRP (i) while operating in a track-following mode, and (ii) during the first revolution. The controller ceases learning of the second RRP when one of (i) the controller is operating in a seek mode and (ii) the rotating storage medium is in an off-track state. Subsequent to the first revolution of the rotating storage medium and based on whether the learning of the second RRP was stopped during the first revolution, the controller replaces the first RRP with the second RRP in the first buffer.
摘要:
A disk drive system-on-chip (SOC) includes a read-channel module and a processor. The read-channel module reads data, includes a first error-correcting module for correcting errors in the data, corrects errors in a first portion of the data using the first error-correcting module, and is unable to correct errors in a second portion of the data using the first error-correcting module. The processor includes a processor core and processor memory, receives the second portion of the data in the processor memory, and corrects errors in the second portion of the data using a second error-correcting module that is different than the first error-correcting module.
摘要:
An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. During sensing of a state of a given memory cell, the bit line decoder (i) precharges a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and (ii) precharges a second bit line of the two corresponding bit lines to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.
摘要:
A method and apparatus is described for reducing RRO in storage systems. A disc may be partitioned into a number of equally spaced sectors. An RRO profile may be individually obtained for each sector, a runout control algorithm may be applied to each sector to generate an RROC waveform for the sector to suppress the RRO, and sector RROC waveforms may be assembled into an RROC waveform for a whole revolution and saved in a memory buffer for feed-forward control. The RROC is performed in the time domain, and it may be adapted for each sector to reject the RRO disturbance.
摘要:
A self-servo writing circuit including a controller. The controller is in communication with a read/write head having a read element and a write element, in which the read element is radially offset from the write element by a first predetermined distance. The controller is configured to i) cause the write element to write a first set of wedges of servo data onto a disk, and ii) after causing the write element to write the first set of wedges of servo data, cause the write element to write a second set of wedges of servo data onto the disk between the first set of wedges of servo data. The second set of wedges of servo data is radially offset from the first set of wedges of servo data based on the first predetermined distance between the read element and the write element.
摘要:
A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values.