公开(公告)号：US07990783B1

公开(公告)日：2011-08-02

申请号：US13004136

申请日：2011-01-11

申请人： Philip Clarke ,  Andrew Bellis ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu

发明人： Philip Clarke ,  Andrew Bellis ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C7/00 ,  H03K19/00 ,  H03K5/12

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

摘要翻译： 将输入寄存器与DQS信号上的虚假转换隔离的电路，方法和设备。 一个示例从核心接收使能信号。 可以称为半周期电路的逻辑电路将其前端的使能脉冲缩短半个周期。 缩短的使能信号被传递到诸如寄存器的存储元件。 缩短的使能信号的有效脉冲清除寄存器，其提供闭合开关的控制信号，例如与门。 当开关闭合时，开关将DQS信号传送到输入寄存器，并在断开时将输入寄存器与DQS信号隔离。 缩短的使能信号防止开关在DQS信号的早期打开和传递寄生跳变，例如在背对背非连续读取周期期间。

公开(公告)号：US07928770B1

公开(公告)日：2011-04-19

申请号：US11935347

申请日：2007-11-05

申请人： Andrew Bellis ,  Philip Clarke ,  Joseph Huang ,  Yan Chong ,  Michael H. M. Chu ,  Manoj B. Roge

发明人： Andrew Bellis ,  Philip Clarke ,  Joseph Huang ,  Yan Chong ,  Michael H. M. Chu ,  Manoj B. Roge

IPC分类号： H03K19/096

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18

摘要： I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

摘要翻译： I / O块包括用于与存储器件连接的输入，输出和输出使能电路。 输入电路包括用于捕获双倍数据速率信号的寄存器，将其转换为单个数据速率信号，并重新同步单个数据速率信号。 多个设备可以被访问，每个设备潜在地具有用于重新同步的不同的时钟信号。 另一个时钟信号可用于对准/同步来自多个设备的结果信号。 再同步的单速率信号可以转换成半速率数据信号，并且可以将四个半速率数据信号提供给可编程器件核心中的资源。 输入电路还可以将半速率数据信号同步的半速率时钟信号提供给可编程器件核心。 半速率时钟信号可以使用数据选通信号，全速率时钟信号或半速率时钟信号作为输入从全速率时钟信号导出。