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    DESIGN STRUCTURE, FAILURE ANALYSIS TOOL AND METHOD OF DETERMINING WHITE BUMP LOCATION USING FAILURE ANALYSIS TOOL
    91.
    发明申请
    DESIGN STRUCTURE, FAILURE ANALYSIS TOOL AND METHOD OF DETERMINING WHITE BUMP LOCATION USING FAILURE ANALYSIS TOOL 有权
    设计结构，故障分析工具和使用故障分析工具确定白色位置的方法

    公开(公告)号：US20090235212A1

    公开(公告)日：2009-09-17

    申请号：US12046608

    申请日：2008-03-12

    申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

    发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.

    摘要翻译： 提供了故障分析工具，使用该工具的方法和设计用于设计用于保护封装期间半导体芯片中的接线故障的关键区域的掩模的设计结构。 故障分析工具包括计算机基础设施，其可操作以通过确定从芯片的中心到焊料凸块处理的位置的距离来确定在焊料凸块形成期间的布线层故障的风险区域，并且识别位置边缘处的区域 用于从芯片的中心预定距离和更大的焊料凸块工艺。

    Chip dicing
    98.
    发明授权
    Chip dicing 失效
    芯片切片

    公开(公告)号：US07112470B2

    公开(公告)日：2006-09-26

    申请号：US10711383

    申请日：2004-09-15

    申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

    发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

    IPC分类号： H01L21/48

    CPC分类号： H01L21/78

    摘要： A semiconductor structure and method for chip dicing. The method comprises the steps of (a) providing a semiconductor substrate; (b) forming first and second device regions of first and second chips, respectively, in and at top of the semiconductor substrate, wherein the first and second chips are separated by a semiconductor border region of the semiconductor substrate; (c) forming N interconnect layers directly above the semiconductor border region and the first and second device regions, wherein N is a positive integer, wherein each layer of the N interconnect layers comprises an etchable portion directly above the semiconductor border region, and wherein the etchable portions of the N interconnect layers form a continuous etchable block; (d) removing the continuous etchable block by etching; and (e) cutting with a laser through the semiconductor border region via an empty space of the removed continuous etchable block to separate the first and second chips.

    摘要翻译： 一种用于芯片切割的半导体结构和方法。 该方法包括以下步骤：（a）提供半导体衬底; （b）分别在半导体衬底中和顶部形成第一和第二芯片的第一和第二器件区域，其中第一和第二芯片由半导体衬底的半导体边界区域分开; （c）在半导体边界区域和第一和第二器件区域正上方形成N个互连层，其中N是正整数，其中N个互连层的每层包括直接在半导体边界区域上方的可蚀刻部分，并且其中 N互连层的可蚀刻部分形成连续的可蚀刻块; （d）通过蚀刻去除连续的可蚀刻块; 以及（e）通过所述被去除的连续可蚀刻块的空白空间，用激光切割所述半导体边界区域以分离所述第一和第二芯片。

    Antifuse for use with low &kgr; dielectric foam insulators
    99.
    发明授权
    Antifuse for use with low &kgr; dielectric foam insulators 失效
    用于低kappa电介质泡沫绝缘子的防腐剂

    公开(公告)号：US06835973B2

    公开(公告)日：2004-12-28

    申请号：US10159573

    申请日：2002-05-31

    申请人： Timothy H. Daubenspeck ,  William A. Klaasen ,  William T. Motsiff ,  Rosemary A. Previti-Kelly ,  Jed H. Rankin

    发明人： Timothy H. Daubenspeck ,  William A. Klaasen ,  William T. Motsiff ,  Rosemary A. Previti-Kelly ,  Jed H. Rankin

    IPC分类号： H01L2710

    CPC分类号： H01L23/5254 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low &kgr; nanopore/nanofoam dielectric material adjacent the conductive line ends.

    摘要翻译： 用于半导体器件的可熔连接件包括在绝缘衬底的表面上的绝缘衬底和导电线对，导电线对具有间隔开的端部。 聚合物设置在绝缘基板之上和导线对端之间。 聚合物能够在暴露于能量束时从非导电状态改变为导电状态。 优选地，聚合物包括聚酰亚胺，更优选聚合物/鎓盐混合物，最优选掺杂有三苯基鎓盐的聚苯胺聚合物。 该连接可以进一步包括邻近导线末端的低kappa纳米孔/纳米电流介电材料。