公开(公告)号：US06928136B2

公开(公告)日：2005-08-09

申请号：US10145033

申请日：2002-05-15

申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H03K19/017 ,  H03K19/096

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

摘要翻译： 提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。 当输入时钟信号CK 1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置于低电平。 然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。 然后，CK 1变为低电平，并且每个TFT（101,103）被关断。 同时，CK 3变为高电平，信号输出部分的电位增加。 同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。 当SP变低时 CK 3变低; 并且CK 1变为高电平时，信号输出部（Out）的电位再次变为低电平。

公开(公告)号：US06909409B2

公开(公告)日：2005-06-21

申请号：US09858627

申请日：2001-05-17

申请人： Yoshifumi Tanada

发明人： Yoshifumi Tanada

IPC分类号： G09G3/20 ,  G09G3/30 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  H01L51/50 ,  G09G3/18

CPC分类号： H01L27/1259 ,  G09G3/2022 ,  G09G3/3225 ,  G09G2300/0465 ,  G09G2300/0842 ,  G09G2300/0861 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/3244 ,  H01L29/78621 ,  H01L2029/7863

摘要： An electro-optical device with a pixel portion of enhanced definition is provided, which uses pixels having a novel structure so that the number of stages of a source signal line side driver circuit is reduced to half the number of pixels in the horizontal direction, thereby making a space for placing the driver circuit and increasing the aperture ratio. One horizontal period is divided into the former half and the latter half. Signals for two adjacent pixels are successively inputted to one source signal line. A pixel selecting portion is provided between the two adjacent pixels. The signal selecting portion selects one of the pixels in the former half of one horizontal period so that a signal is written in the pixel whereas it selects the other pixel during the latter half of the horizontal period so that a signal is written in the pixel. Since one source signal line is shared between two adjacent pixels, the invention is advantageous also in terms of aperture ratio.

摘要翻译： 提供了具有增强的清晰度的像素部分的电光装置，其使用具有新颖结构的像素，使得源信号线侧驱动电路的级数减少到水平方向上的像素数量的一半，由此 形成放置驱动电路的空间并增加开口率。 一个水平时期分为前半部分和后半部分。 两个相邻像素的信号被连续地输入到一个源信号线。 像素选择部分设置在两个相邻像素之间。 信号选择部分选择一个水平周期的前半部分中的一个像素，使得信号被写入像素，而在水平周期的后一半期间选择另一个像素，使得信号被写入像素。 由于一个源极信号线在两个相邻像素之间共享，所以本发明在孔径比方面也是有利的。

公开(公告)号：US20050051776A1

公开(公告)日：2005-03-10

申请号：US10867226

申请日：2004-06-15

申请人： Noriko Miyagi ,  Masayuki Sakakura ,  Tatsuya Arao ,  Ritsuko Nagao ,  Yoshifumi Tanada

发明人： Noriko Miyagi ,  Masayuki Sakakura ,  Tatsuya Arao ,  Ritsuko Nagao ,  Yoshifumi Tanada

IPC分类号： G09G3/32 ,  H01L27/32 ,  H01L29/04 ,  H01L51/52

CPC分类号： H01L27/124 ,  G02F1/133345 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2300/0861 ,  H01L23/5228 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/3276 ,  H01L27/3279 ,  H01L33/40 ,  H01L51/5206 ,  H01L51/5212 ,  H01L51/5221 ,  H01L51/5228 ,  H01L51/5234 ,  H01L2251/5315

摘要： An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive material than the resistance of an electrode and a wiring that is required to reduce the resistance.

摘要翻译： 本发明的一个目的是降低诸如透明电极或布线的电极的实质电阻，此外，提供一种可以向发光元件施加相同电压的显示装置。 在本发明中，形成在电极，布线，信号线，扫描线或电源线等半导体元件的导电膜的一层中形成的辅助布线连接到以 第二电极和布线。 优选地，辅助布线形成为包括低电阻材料的导电膜，特别地，形成为包括比电阻的阻抗更低的电阻材料和降低电阻所需的布线。

公开(公告)号：US20050035805A1

公开(公告)日：2005-02-17

申请号：US10807692

申请日：2004-03-24

申请人： Yoshifumi Tanada

发明人： Yoshifumi Tanada

IPC分类号： G01R31/28 ,  G09G3/00 ,  G09G3/20 ,  G06F1/04

CPC分类号： G09G3/20 ,  G01R31/2853 ,  G09G3/006 ,  G09G2330/12

摘要： It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is connected to one input terminal of a NAND circuit and a NOR circuit, and an output of an inspection is obtained from final lines of the NAND circuit and the NOR circuit connected in series. In this manner, an inspecting circuit which is capable of determining a defect simply and accurately by using a small-scale circuit, and a method thereof are provided.

摘要翻译： 通过多个反相器串联连接的多个NAND电路以及通过多个逆变器串联连接的多个NOR电路构成。 设置在像素部分中的多个源极信号线中的每一个连接到NAND电路和NOR电路的一个输入端，并且从串联连接的NAND电路和NOR电路的最后一行获得检查的输出 。 以这种方式，提供了能够通过使用小规模电路简单且准确地确定缺陷的检查电路及其方法。

公开(公告)号：US09443461B2

公开(公告)日：2016-09-13

申请号：US12509228

申请日：2009-07-24

申请人： Hajime Kimura ,  Yoshifumi Tanada

发明人： Hajime Kimura ,  Yoshifumi Tanada

IPC分类号： G09G3/30 ,  G09G3/20 ,  G09G3/32 ,  H01L51/52

CPC分类号： G09G3/3258 ,  G09G3/2018 ,  G09G3/2022 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/0876 ,  G09G2310/0262 ,  G09G2310/061 ,  G09G2310/08 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L51/525 ,  H01L2227/323

摘要： To provide a novel driving method for driving an electronic device by using digital gray scale and time gray scale in combination, which secures high duty ratio, which can display an image normally even when a sustain period is shorter than an address period, and which is hardly affected by dulled signal waveform. In a sub-frame period (102) where a sustain period is shorter than an address period, a clear period (105) is squeezed in between completion of a sustain period (104) and start of an address period of the subsequent sub-frame period. The length of the sustain period (104) thus can be set without being limited by the length of an address period (103). This non-display period is provided by changing the electric potential of a storage capacitor line. Therefore, unlike the case where the non-display period is provided by changing the electric potential of a cathode wiring, the present invention is hardly affected by dulled signal waveform.

公开(公告)号：US20130057161A1

公开(公告)日：2013-03-07

申请号：US13604709

申请日：2012-09-06

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： H05B37/02

CPC分类号： G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

摘要： A pulse is input to first and second TFTs to turn ON the first and second TFTs so that the potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α enters a floating state. Accordingly, a third TFT then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the third TFT further rises due to an operation of capacitance as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the third TFT.

摘要翻译： 脉冲被输入到第一和第二TFT以接通第一和第二TFT，使得节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α进入浮动状态。 因此，第三TFT然后导通，并且输出节点的电位随着时钟信号达到电平H而升高。另一方面，由于作为电位的电容的操作，第三TFT的栅电极的电位进一步上升 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，输出节点的电位上升到VDD而没有由第三TFT的阈值引起的电压降。

公开(公告)号：US08310433B2

公开(公告)日：2012-11-13

申请号：US13085522

申请日：2011-04-13

申请人： Yoshifumi Tanada ,  Tadafumi Ozaki

发明人： Yoshifumi Tanada ,  Tadafumi Ozaki

IPC分类号： G09G3/36

CPC分类号： G09G3/3225 ,  G09G3/2022 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2300/08 ,  G09G2300/0809 ,  G09G2310/063 ,  G09G2320/041 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/18

摘要： The invention provides a display device and an electronic apparatus which can reduce power consumption in the case of being driven by using a digital time grayscale method. According to the invention, a row in which all the pixels display black is focused on in a plurality of pixels arranged in matrix, and sampling of data which is to be inputted to the pixels arranged in the row is not performed. Then, in a period during which the data sampling is not performed, the operation of a shift register in a source driver and, sampling operation of a video signal in a first latch circuit are stopped. The invention which has the aforementioned characteristics can temporally stop operation of the source driver to reduce power consumption. In particular, the invention can stop operation of the source driver which consumes much power in the display device, leading to dramatic reduction in power consumption.

摘要翻译： 本发明提供了一种显示装置和电子装置，其可以通过使用数字时间灰度方法驱动的情况下降低功耗。 根据本发明，在矩阵排列的多个像素中集中了所有像素显示黑色的行，并且不执行要输入到排列在行中的像素的数据的采样。 然后，在不执行数据采样的期间，停止源极驱动器中的移位寄存器的操作，以及第一锁存电路中的视频信号的采样操作。 具有上述特征的本发明可以暂时停止源极驱动器的运行以降低功耗。 特别地，本发明可以停止在显示装置中消耗大量功率的源驱动器的操作，导致功耗的显着降低。

公开(公告)号：US20120205700A1

公开(公告)日：2012-08-16

申请号：US13367833

申请日：2012-02-07

申请人： Yoshifumi Tanada ,  Naoya Sakamoto ,  Hiroki Adachi ,  Shingo Eguchi ,  Koji Ono ,  Kensuke Yoshizumi ,  Hiroto Shinoda

发明人： Yoshifumi Tanada ,  Naoya Sakamoto ,  Hiroki Adachi ,  Shingo Eguchi ,  Koji Ono ,  Kensuke Yoshizumi ,  Hiroto Shinoda

IPC分类号： H01L51/52 ,  H01L51/56

CPC分类号： H01L51/5212 ,  H01L27/3279 ,  H01L51/5228 ,  H01L2251/5361

摘要： The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device.

摘要翻译： 本发明的重点是在基板侧设置用于提高上部电极的导电性的辅助布线的结构。 发光装置的导电性辅助布线设置在基板上，辅助配线的上部沿与基板平行的方向突出。 此外，在包括下电极层和辅助布线的区域中形成的EL层在物理上被辅助布线分开。 以类似于下电极层的方式形成的上电极层可以电连接到辅助布线的侧表面的至少一部分。 这种辅助布线可以用在照明装置和显示装置中。

公开(公告)号：US08115160B2

公开(公告)日：2012-02-14

申请号：US12398465

申请日：2009-03-05

申请人： Jun Koyama ,  Yoshifumi Tanada ,  Hideaki Shishido

发明人： Jun Koyama ,  Yoshifumi Tanada ,  Hideaki Shishido

IPC分类号： H03K17/78 ,  H01J40/14 ,  H02H9/00

CPC分类号： H02H9/04 ,  H02H7/20 ,  Y02E10/56

摘要： A protection circuit and a photoelectric conversion device are provided, each of which includes a first wiring, a second wiring, a first switch, a second switch, a capacitor, and a comparing circuit configured to generate a signal corresponding to a potential of the first wiring and a potential of the second wiring, and supply the signal to the first switch and the second switch. The first wiring is electrically connected to a first terminal of the first switch, and the second wiring is electrically connected to a first terminal of the second switch. A second terminal of the first switch is electrically connected to a first electrode of the capacitor, and a second terminal of the second switch is electrically connected to a second electrode of the capacitor.

摘要翻译： 提供一种保护电路和光电转换装置，每个保护电路和光电转换装置包括第一布线，第二布线，第一开关，第二开关，电容器和比较电路，其被配置为产生对应于第一布线 布线和第二布线的电位，并将信号提供给第一开关和第二开关。 第一布线电连接到第一开关的第一端子，第二布线电连接到第二开关的第一端子。 第一开关的第二端子电连接到电容器的第一电极，并且第二开关的第二端子电连接到电容器的第二电极。

公开(公告)号：US08054596B2

公开(公告)日：2011-11-08

申请号：US12400380

申请日：2009-03-09

申请人： Jun Koyama ,  Yoshifumi Tanada ,  Hideaki Shishido

发明人： Jun Koyama ,  Yoshifumi Tanada ,  Hideaki Shishido

IPC分类号： H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC分类号： H01L27/0251 ,  G02F1/136204

摘要： An element is protected without hampering an actual operation in the case where overvoltage that might damage the element is applied. A semiconductor device includes a first potential supply terminal 100; a second potential supply terminal 101; a protection circuit 107 which includes a voltage divider 102 electrically connected to the first potential supply terminal 100 and the second potential supply terminal 101, a control circuit 103, and a bypass circuit 106; and a functional circuit 108 which is electrically connected to the first potential supply terminal 100 and the second potential supply terminal 101 through the protection circuit 107.

摘要翻译： 在可能损坏元件的过电压被施加的情况下，元件被保护而不妨碍实际操作。 半导体器件包括第一电位供给端子100; 第二电位供给端子101; 保护电路107，其包括电连接到第一电位端子100和第二电位端子101的分压器102，控制电路103和旁路电路106; 以及通过保护电路107与第一电位供给端子100和第二电位供给端子101电连接的功能电路108。