公开(公告)号：US09075340B2

公开(公告)日：2015-07-07

申请号：US13494696

申请日：2012-06-12

申请人： Kenichi Kuroda ,  Akihiko Kawatani ,  Yoshihisa Mizumoto

发明人： Kenichi Kuroda ,  Akihiko Kawatani ,  Yoshihisa Mizumoto

IPC分类号： G03G15/08 ,  G03G13/20

CPC分类号： G03G15/0818 ,  G03G13/20 ,  G03G2215/0861

摘要： An inventive developing roller is adapted for use in an electrophotographic image forming apparatus. The developing roller includes a roller body. At least an outer peripheral surface of the roller body is formed from a rubber composition containing a base rubber. The base rubber contains a styrene butadiene rubber in a proportion of not less than 10 mass % and not greater than 70 mass % based on the overall amount of the base rubber. The outer peripheral surface of the rubber body has a surface roughness Ra of not less than 0.78 μm and not greater than 1.8 μm.

摘要翻译： 本发明的显影辊适用于电子照相成像设备。 显影辊包括辊体。 辊体的至少外周面由含有基础橡胶的橡胶组合物形成。 基础橡胶含有基于橡胶总量不小于10质量％且不大于70质量％的丁苯橡胶。 橡胶体的外周面的表面粗糙度Ra为0.78μm以上且1.8μm以下。

公开(公告)号：US08670700B2

公开(公告)日：2014-03-11

申请号：US13559987

申请日：2012-07-27

申请人： Kenichi Kuroda ,  Akihiko Kawatani ,  Masakazu Tanaka ,  Yoshihisa Mizumoto

发明人： Kenichi Kuroda ,  Akihiko Kawatani ,  Masakazu Tanaka ,  Yoshihisa Mizumoto

IPC分类号： G03G15/08

CPC分类号： G03G15/0818

摘要： A developing roller is provided, which is particularly used in an image forming apparatus of a highly durable design and is free from toner leakage even after formation of a predetermined number of images. Opposite end regions (5a) of an outer peripheral surface (5) of a roller body (2) of the developing roller (1) to be respectively kept in sliding contact with seal members each have a friction coefficient μ of not greater than 0.15.

摘要翻译： 提供了一种显影辊，其特别用于高度耐用设计的图像形成装置中，即使在形成预定数量的图像之后也不会有调色剂泄漏。 与密封件分别保持滑动接触的显影辊（1）的辊体（2）的外周面（5）的相对的端部区域（5a）各自具有不大于0.15的摩擦系数μ。

公开(公告)号：US07965563B2

公开(公告)日：2011-06-21

申请号：US12320679

申请日：2009-02-02

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US07505329B2

公开(公告)日：2009-03-17

申请号：US11860762

申请日：2007-09-25

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

公开(公告)号：US20080139701A1

公开(公告)日：2008-06-12

申请号：US11792137

申请日：2005-12-02

申请人： Wernher M Danzinger ,  Kaname Saitoh ,  Tetsu Tomoyose ,  Atsushi Kobayashi ,  Akira Ikeda ,  Kenichi Kuroda

发明人： Wernher M Danzinger ,  Kaname Saitoh ,  Tetsu Tomoyose ,  Atsushi Kobayashi ,  Akira Ikeda ,  Kenichi Kuroda

IPC分类号： C08K3/36

CPC分类号： C04B24/2647 ,  C04B24/2658 ,  C04B24/2694 ,  C04B40/0042 ,  C04B2103/0057 ,  C04B2103/302 ,  C04B2103/308 ,  C04B2103/408 ,  C04B14/06 ,  C04B20/008 ,  C04B2103/50

摘要： There is provided a powdered polycarboxylic acid-based cement dispersant containing a polyamide-polyamine in a skeleton of a polymer thereof and a dispersant composition containing the dispersant, the dispersant having improved water reducing ability, slump-flow retention, and strength-developing properties of concrete, enabling effective prevention of blocking, being highly soluble in a slurry, and being homogeneously mixed with an inorganic powder. The powdered polycarboxylic acid-based cement dispersant comprises a powdered cement dispersant obtained by dry-powdering a solution or dispersion of a copolymer containing a polyamide-polyamine in a skeleton of a polymer thereof, wherein the powder has a sphere form, an average particle diameter of 30 to 300 μm, and a particle size distribution in which the mass of particles having a particle diameter of 50 to 350 μm accounts for 70% or more of the total mass of the powder.

摘要翻译： 在聚合物的骨架中提供含有聚酰胺 - 多胺的粉末状多元羧酸类水泥分散剂和含有分散剂的分散剂组合物，具有改善的减水能力的分散剂，坍落度流动保持性和强度显现性 混凝土，能够有效地防止堵塞，高度溶于浆料，并与无机粉末均匀混合。 粉状多元羧酸类水泥分散剂包括粉末状水泥分散剂，其通过将含有聚酰胺 - 多胺的共聚物的溶液或分散体在其聚合物的骨架中干粉末而得到，其中粉末具有球形，平均粒径 为30〜300μm的粒子，粒径为50〜350μm的粒子的质量占粉末总质量的70％以上的粒度分布。

公开(公告)号：US20070171692A1

公开(公告)日：2007-07-26

申请号：US11727693

申请日：2007-03-28

申请人： Kenichi Kuroda ,  Toshifumi Takeda ,  Hisahiro Moriuchi ,  Masaki Shirai ,  Jiroh Sakaguchi ,  Akinori Matsuo ,  Shoji Yoshida

发明人： Kenichi Kuroda ,  Toshifumi Takeda ,  Hisahiro Moriuchi ,  Masaki Shirai ,  Jiroh Sakaguchi ,  Akinori Matsuo ,  Shoji Yoshida

IPC分类号： G11C17/00

CPC分类号： H01L27/11526 ,  G11C16/0408 ,  G11C16/10 ,  G11C29/789 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11546

摘要： A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

摘要翻译： 单层栅型结构的非易失性存储元件被布置成使得浮置栅极由与扩散层形成的控制栅极部分重叠的导电层形成，并且设置有覆盖部分的阻挡层 或浮动门的整个表面。 其特征在于的非易失性存储元件用于缺陷的冗余控制或功能的改变。

公开(公告)号：US20070133308A1

公开(公告)日：2007-06-14

申请号：US11657473

申请日：2007-01-25

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

公开(公告)号：US07184321B2

公开(公告)日：2007-02-27

申请号：US11245338

申请日：2005-10-07

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

公开(公告)号：US07002830B2

公开(公告)日：2006-02-21

申请号：US10694085

申请日：2003-10-28

申请人： Kenichi Kuroda ,  Toshifumi Takeda ,  Hisahiro Moriuchi ,  Masaki Shirai ,  Jiroh Sakaguchi ,  Akinori Matsuo ,  Shoji Yoshida

发明人： Kenichi Kuroda ,  Toshifumi Takeda ,  Hisahiro Moriuchi ,  Masaki Shirai ,  Jiroh Sakaguchi ,  Akinori Matsuo ,  Shoji Yoshida

IPC分类号： G11C7/00

CPC分类号： H01L27/11526 ,  G11C16/0408 ,  G11C16/10 ,  G11C29/789 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11546

摘要： A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

公开(公告)号：US20060034129A1

公开(公告)日：2006-02-16

申请号：US11245338

申请日：2005-10-07

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C16/04 ,  G06F12/00

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.