公开(公告)号：US20190138312A1

公开(公告)日：2019-05-09

申请号：US16239766

申请日：2019-01-04

Applicant: International Business Machines Corporation

Inventor： RICHARD J. EICKEMEYER ,  SHELDON LEVENSTEIN ,  DAVID S. LEVITAN ,  MAURICIO J. SERRANO

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0862

CPC classification number: G06F9/3802 ,  G06F9/3891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/6026

Abstract: Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

公开(公告)号：US20180300145A1

公开(公告)日：2018-10-18

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0811 ,  G06F12/0855 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/455 ,  G06F2212/602 ,  G06F2212/6024 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US20180276140A1

公开(公告)日：2018-09-27

申请号：US15616917

申请日：2017-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eric C. QUINNELL ,  Kevin C. HEUER ,  Tarun NAKRA ,  Akhil ARUNKUMAR

IPC: G06F12/123 ,  G06F12/0891 ,  G06F12/0815 ,  G06F12/0862

CPC classification number: G06F12/123 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F2212/602 ,  G06F2212/621

Abstract: Embodiments of the present system and method provide cache replacement in a victim exclusive cache using a snoop filter where replacement information is not lost during a re-reference back to the CPU. Replacement information is stored in a snoop filter, meaning that historical access data may be fully preserved and allows for more flexibility in the LLC re-insertion points, without additional bits stored in a L2 cache. The present system and method further include snoop filter replacement technique. The present system and method passes replacement information between a snoop filter and a victim exclusive cache (e.g., LLC) when transactions move cachelines to and from a master CPU. This maintains and advances existing replacement information for a cacheline that is removed from the victim exclusive cache on a read, as well as intelligently replaces and ages cachelines in the snoop filter.

公开(公告)号：US20180275886A1

公开(公告)日：2018-09-27

申请号：US15469157

申请日：2017-03-24

Applicant: Veritas Technologies LLC

Inventor： Xianbo Zhang ,  Weibao Wu ,  Jeffrey Van Voorst ,  Haigang Wang ,  Yong Yang ,  Shuangmin Zhang

IPC: G06F3/06 ,  G06F12/0862

CPC classification number: G06F3/0608 ,  G06F3/0611 ,  G06F3/0643 ,  G06F3/0685 ,  G06F12/0862

Abstract: The disclosed computer-implemented method for data placement in container-based storage systems may include (i) identifying a file stored within a container-based storage system, where the container-based storage system stores the file as data segments within containers, (ii) receiving, in response to a write operation directed to the file, a request to store within the container-based storage system a new data segment generated by the write operation, (iii) describing the file in terms of a plurality of consecutive slabs, (iv) determining that the new data segment falls within a specified slab, and (v) fulfilling the request to store the new data segment within the container-based storage system by storing the new data segment in a designated container that corresponds to the specified slab in response to determining that the new data segment falls within the specified slab. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US10078547B2

公开(公告)日：2018-09-18

申请号：US15275651

申请日：2016-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Raymond Wong ,  Jie Zheng

IPC: H03M13/00 ,  G06F11/10 ,  G06F12/0862

CPC classification number: G06F11/1064 ,  G06F11/1004 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1032 ,  G06F2212/602

Abstract: Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

公开(公告)号：US10073697B2

公开(公告)日：2018-09-11

申请号：US15047023

申请日：2016-02-18

Applicant: International Business Machines Corporation

Inventor： Sundeep Chadha ,  Robert A. Cordes ,  David A. Hrusecky ,  Hung Q. Le ,  Jentje Leenstra ,  Dung Q. Nguyen ,  Brian W. Thompto ,  Albert J. Van Norstrand, Jr.

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0862 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F9/30047 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0042

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

公开(公告)号：US10067706B2

公开(公告)日：2018-09-04

申请号：US15086882

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan

IPC: G06F12/08 ,  G06F12/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0875 ,  H03M7/30 ,  H03M13/00 ,  G06F12/0862 ,  G06F12/12

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/0223 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/403 ,  G06F2212/466 ,  H03M7/30 ,  H03M13/6312 ,  Y02D10/13

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides a CI hint directory comprising a plurality of CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller is configured to receive a memory read request comprising a physical address of a memory line, and initiate a memory read transaction comprising a requested read length value. The compressed memory controller is further configured to, in parallel with initiating the memory read transaction, determine whether the physical address corresponds to a CI hint directory entry in the CI hint directory. If so, the compressed memory controller reads a CI hint from the CI hint directory entry of the CI hint directory, and modifies the requested read length value of the memory read transaction based on the CI hint.

公开(公告)号：US20180232313A1

公开(公告)日：2018-08-16

申请号：US15882104

申请日：2018-01-29

Applicant: ARM Limited

Inventor： Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Jonas SVEDAS ,  Stephan DIESTELHORST

IPC: G06F12/0871 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0808 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/0871 ,  G06F3/064 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0895 ,  G06F2212/6026

Abstract: A system cache and method of operating a system cache are provided. The system cache provides data caching in response to data access requests from plural system components. The system cache has data caching storage with plural entries, each entry storing a block of data items and each block of data items comprising plural sectors of data items, and each block of data items being stored in an entry of the data caching storage with an associated address portion. Sector use prediction circuitry is provided which has a set of pattern entries to store a set of sector use patterns. In response to a data access request received from a system component specifying one or more data items a selected pattern entry is selected in dependence on a system component identifier in the data access request and a sector use prediction is generated in dependence on a sector use pattern in the selected pattern entry. Further data items may then be retrieved which are not specified in the data access request but are indicated by the sector use prediction, and memory bandwidth usage is thereby improved.

公开(公告)号：US20180225122A1

公开(公告)日：2018-08-09

申请号：US15879492

申请日：2018-01-25

Applicant: FUJITSU LIMITED

Inventor： Tatsuo Kumano

IPC: G06F9/38 ,  G06F12/0866 ,  G06F12/0862 ,  G06F3/06

CPC classification number: G06F9/3832 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/312 ,  G06F2212/604

Abstract: A method performed by a computer for analyzing access to a storage device, the method includes: executing a calculating process that includes calculating, for each of a plurality of ranges obtained by dividing a storage area of the storage device, an access number or a variation of the access number in each of a plurality of periods, wherein the access number indicates the number of times of access to each of the plurality of ranges; and executing a determining process that includes determining a correlation between any two of the plurality of ranges in accordance with the access number or the variation of the access number for each period in each of the plurality of ranges.

公开(公告)号：US10037280B2

公开(公告)日：2018-07-31

申请号：US14726454

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Meghal Varia ,  Serag Gadelrab ,  Muhammad Umar Choudry

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0862 ,  G06F12/109

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/507 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/654

Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.