公开(公告)号：US07433997B2

公开(公告)日：2008-10-07

申请号：US11240632

申请日：2005-10-03

Applicant: Gannady Lapir ,  Harry Urbshat

Inventor： Gannady Lapir ,  Harry Urbshat

IPC: G06F12/00

CPC classification number: G06F17/30637 ,  G06F17/30979 ,  G06F17/30982 ,  G11C15/00 ,  G11C15/043 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and according to the rules used for generating the feature vectors corresponding to the stored document s such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more additional result columns coding for a similarity measure between the query and parts or the whole of the stored documents; and said method further comprising one or a combination of the following: retrieval of one or more stores documents based on the obtained similarity measure; and or storing a representation of a document through it s feature vector into the above matrix.

Abstract translation: 一种实现能够存储文档集合并且与输入的查询文档类似的一个或多个存储文档的计算机实现的方法，所述方法包括：通过相应的特征向量对每个文档或其一部分进行编码，该特征向量包括 分别编码所述文档中某些特征的存在或不存在的一系列位; 将特征向量排列成矩阵; 基于查询文档生成查询特征向量，并根据用于生成与存储文档对应的特征向量的规则，使得查询向量的长度与矩阵的宽度相对应; 逐列存储矩阵; 对于矩阵的那些列，其中查询向量指示特征的存在，在矩阵的列之间按位地执行优选地由硬件支持的逻辑运算中的一个或多个，以获得编码查询之间的相似性度量的一个或多个附加结果列 部分或全部存放文件; 并且所述方法还包括以下的一个或组合：基于所获得的相似性度量检索一个或多个存储文档; 和/或通过其将文档的表示存储到上述矩阵中。

公开(公告)号：US20080179651A1

公开(公告)日：2008-07-31

申请号：US11882166

申请日：2007-07-31

Applicant: Atsushi Amo ,  Shunji Kubo

Inventor： Atsushi Amo ,  Shunji Kubo

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C15/043 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract translation: 为了提高从匹配线的电位的放电速度，半导体器件包括电容器，具有连接到电容器的存储节点的源极/漏极区域的存储晶体管，具有连接到存储器的栅电极的搜索晶体管 以及连接匹配线和搜索晶体管的源极/漏极区域的堆叠接触。 存储节点具有这样的配置，其中面向匹配线的存储节点的侧壁部分地从堆叠的接触件中退出，使得沿着匹配线的方向的平面图中的层叠接触件前面的侧壁的一部分位于 比侧壁的剩余部分更远离堆叠的接触。

公开(公告)号：US20080049481A1

公开(公告)日：2008-02-28

申请号：US11877310

申请日：2007-10-23

Applicant: Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajgaya

Inventor： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajgaya

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/043

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract translation: 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

公开(公告)号：US20080025059A1

公开(公告)日：2008-01-31

申请号：US11787667

申请日：2007-04-17

Applicant: Robert McKenzie ,  Dieter Haerle ,  Sean Lord

Inventor： Robert McKenzie ,  Dieter Haerle ,  Sean Lord

IPC: G11C15/00

CPC classification number: G11C15/043 ,  G11C15/00 ,  G11C15/04

Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.

Abstract translation: 内容可寻址存储器阵列包括以行和列排列的多个耦合子块。 由CAM的第一列中的第一子块接收的搜索数据被传播到该CAM的最后一列中的行中的每个子块到最后一个子块。 基于每行子块的传播搜索结果选择CAM的搜索结果，并在与接收搜索数据的一侧相反的阵列的一侧上输出。

公开(公告)号：US20070258277A1

公开(公告)日：2007-11-08

申请号：US11774881

申请日：2007-07-09

Applicant: Stanley Ma ,  Peter Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

Inventor： Stanley Ma ,  Peter Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC: G11C15/00

CPC classification number: G11C7/06 ,  G11C15/04 ,  G11C15/043

Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

Abstract translation: 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前，该电路首先将匹配线预先接地，并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后，匹配线上的感测数据将被锁存，并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD，所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位，匹配线感测操作速度增加。

公开(公告)号：US20070195570A1

公开(公告)日：2007-08-23

申请号：US11361947

申请日：2006-02-23

Applicant: Laurence Hager Cooke

Inventor： Laurence Hager Cooke

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/043

Abstract: A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also presented.

Abstract translation: 提出了一种使用传统存储器实现内容可寻址存储器（CAM）功能的技术，其中输入数据被串行加载到串行CAM中。 还提出了允许预测与串行输入数据的完成一致的串行CAM访问的结果的各种添加。

公开(公告)号：US20070133258A1

公开(公告)日：2007-06-14

申请号：US11307318

申请日：2006-02-01

Applicant: Juhan Kim

Inventor： Juhan Kim

IPC: G11C11/24

CPC classification number: G11C11/24 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/12 ,  G11C11/22 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4067 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C15/043 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2213/72 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1023 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1203 ,  H01L27/1214

Abstract: Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; a floating plate capacitor serves as a storage device, wherein the capacitor includes three plates, the first plate is connected to the storage node, the second plate is floating and the third plate is connected to a plate line; when write, the diode determines whether the storage node is coupled or not by raising the plate line; when read, the diode serves as a sense amplifier to detect the storage node voltage whether it is forward bias or not, and the diode sends binary results to a data latch including a current mirror; and the memory is formed on the bulk and SOI wafer.

公开(公告)号：US20070133250A1

公开(公告)日：2007-06-14

申请号：US11308097

申请日：2006-03-07

Applicant: Juhan Kim

Inventor： Juhan Kim

IPC: G11C13/00

CPC classification number: G11C11/24 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/12 ,  G11C11/22 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4067 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C15/043 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2213/72 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1023 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1203 ,  H01L27/1214

Abstract: Phase change memory including diode access device is realized, wherein includes a chalcogenide storage element and a diode access device instead of MOS device, the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to one side of the storage element, the third terminal is floating, the fourth terminal is connected to a bit line, and the other side of the storage element is connected to a resistor line which has floating state just before the word line is asserted to establish the current path of the memory cell. Replica delay circuit controls the read path, which minimizes the read current pulse, induces less current disturbance to the stored data, makes the read access time fast and reduces the current consumption. And the word line cuts off the holding current during standby. Additionally, planar and vertical cell structures are devised on the bulk and SOI wafer.

Abstract translation: 实现了包括二极管存取装置的相变存储器，其中包括硫族化物存储元件和二极管存取装置代替MOS器件，二极管具有四个端子，第一端子连接到字线，第二端子连接到一侧 存储元件的第三端子是浮置的，第四端子连接到位线，并且存储元件的另一侧连接到刚好在字线被断言之前具有浮置状态的电阻线以建立电流 存储单元的路径。 复制延迟电路控制读取路径使读取电流脉冲最小化，对存储的数据引起更少的电流干扰，使读取访问时间快速并减少电流消耗。 并且字线在待机期间切断保持电流。 另外，在体晶片和SOI晶片上设计了平面和垂直单元结构。

公开(公告)号：US20070055818A1

公开(公告)日：2007-03-08

申请号：US11595370

申请日：2006-11-08

Applicant: Brent Keeth ,  Brian Shirley ,  Charles Dennison

Inventor： Brent Keeth ,  Brian Shirley ,  Charles Dennison

IPC: G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, each of which may be refreshed under control of a refresh controller. In addition to the usual components of a DRAM, the cache memory system also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in the second bank. If, however, the second bank is being refreshed, the data are stored in the other SRAM. By the time data have been stored in the SRAM, the SRAM previously used to store write data has transferred the data to the first DRAM bank and in thus available to store a subsequent write. Therefore, an SRAM bank is always available to store write data in the event the DRAM bank to which the data are directed is being refreshed.

Abstract translation: 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，每个存储体可以在刷新控制器的控制下刷新。 除了DRAM的通常部件之外，高速缓冲存储器系统还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传送期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体中。 然而，如果第二个银行被刷新，则数据被存储在另一个SRAM中。 在数据已经存储在SRAM中的时候，先前用于存储写入数据的SRAM已将数据传送到第一DRAM存储体，并因此可用于存储随后的写入。 因此，在刷新数据所指向的DRAM组的情况下，SRAM存储体总是可用于存储写入数据。

公开(公告)号：US20060212431A1

公开(公告)日：2006-09-21

申请号：US11240632

申请日：2005-10-03

Applicant: Gannady Lapir ,  Harry Urbschat

Inventor： Gannady Lapir ,  Harry Urbschat

IPC: G06F7/00

CPC classification number: G06F17/30637 ,  G06F17/30979 ,  G06F17/30982 ,  G11C15/00 ,  G11C15/043 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and according to the rules used for generating the feature vectors corresponding to the stored document s such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more additional result columns coding for a similarity measure between the query and parts or the whole of the stored documents; and said method further comprising one or a combination of the following: retrieval of one or more stores documents based on the obtain ed similarity measure; and or storing a representation of a document through it s feature vector into the above matrix.

Abstract translation: 一种实现能够存储文档集合并且与输入的查询文档类似的一个或多个存储文档的计算机实现的方法，所述方法包括：通过相应的特征向量对每个文档或其一部分进行编码，该特征向量包括 分别编码所述文档中某些特征的存在或不存在的一系列位; 将特征向量排列成矩阵; 基于查询文档生成查询特征向量，并根据用于生成与存储文档对应的特征向量的规则，使得查询向量的长度与矩阵的宽度相对应; 逐列存储矩阵; 对于矩阵的那些列，其中查询向量指示特征的存在，在矩阵的列之间按位地执行优选地由硬件支持的逻辑运算中的一个或多个，以获得编码查询之间的相似性度量的一个或多个附加结果列 部分或全部存放文件; 并且所述方法还包括以下的一个或组合：基于获得的相似性度量检索一个或多个存储文档; 和/或通过其将文档的表示存储到上述矩阵中。