公开(公告)号：US06511894B2

公开(公告)日：2003-01-28

申请号：US10056009

申请日：2002-01-28

申请人： Hoon Song

发明人： Hoon Song

IPC分类号： H01L2130

CPC分类号： B81B7/007 ,  B81B2201/01 ,  H01H59/0009

摘要： A MEMS relay is provided. The MEMS relay includes a first wafer, a second wafer, and a third wafer that are sequentially stacked. The first wafer includes driving electrodes positioned at the bottom surface of the first wafer, input signal electrodes and output signal electrodes formed adjacent to each other and corresponding to the driving electrodes, via holes formed through the first wafer on the driving electrodes, the input signal electrodes, and the output signal electrodes, and metal pads formed over the via holes. The second wafer includes a body including a sealing unit used to hermetically seal the first and third wafers with the second wafer interposed therebetween, a driving unit which is formed inside and isolated from the body, is an integrated body consisting of a silicon substrate, a passivation layer formed on the silicon substrate, and contact electrodes formed on the passivation layer, and is located lower than the top surface of the body by a predetermined distance, and a connection supporter which extends from two opposing sides of the driving unit to the inner surface of the body. The third wafer includes a hollow in which the driving unit can be rotated.

摘要翻译： 提供了MEMS继电器。 MEMS继电器包括依次层叠的第一晶片，第二晶片和第三晶片。 第一晶片包括位于第一晶片的底表面处的驱动电极，输入信号电极和彼此相邻形成并对应于驱动电极的输出信号电极，通过驱动电极上的第一晶片形成的通孔，输入信号 电极和输出信号电极以及形成在通孔上方的金属焊盘。 第二晶片包括主体，其包括用于密封第一晶片和第三晶片的密封单元，其间插入有第二晶片，形成在主体内部并与主体隔离的驱动单元是由硅基板， 形成在硅衬底上的钝化层和形成在钝化层上的接触电极，并且位于比主体的顶表面低一个预定距离处;以及连接支撑件，其从驱动单元的两个相对侧延伸到内部 身体表面。 第三晶片包括可驱动驱动单元旋转的中空部。

公开(公告)号：US06500733B1

公开(公告)日：2002-12-31

申请号：US09957132

申请日：2001-09-20

申请人： Billy J. Stanbery

发明人： Billy J. Stanbery

IPC分类号： H01L2130

CPC分类号： C23C14/5846 ,  C23C14/0005 ,  C23C14/5886 ,  C23C14/5893 ,  C23C26/00 ,  H01L31/0322 ,  H01L31/0749 ,  H01L31/1892 ,  Y02E10/541 ,  Y02P70/521 ,  Y10T156/1111

摘要： Systems and methods are described for synthesis of films, coatings or layers using precursor exerted pressure containment. A method includes exerting a pressure between a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

摘要翻译： 描述了使用前体施加的压力容纳来合成膜，涂层或层的系统和方法。 一种方法包括在耦合到第一衬底的第一前体层和耦合到第二衬底的第二前体层之间施加压力; 形成组合物层; 并且相对于第二基底移动第一基底，其中组合物层保持与第二基底结合。

公开(公告)号：US06468880B1

公开(公告)日：2002-10-22

申请号：US09805954

申请日：2001-03-15

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2130

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  Y10S438/977

摘要： A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.

摘要翻译： 一种使用晶片接合形成绝缘体上硅（SOI）器件的方法。 提供第一基板，其在第一侧上具有绝缘层。 提供了第二衬底，其具有填充第二衬底中的第一沟槽的第一隔离区域（例如STI）。 接下来，通过将绝缘层粘合到第一隔离区域和第二基板上，将第一和第二基板结合在一起。 然后，在第二基板的第二侧上形成止挡层。 图案化第二基板的阻挡层和第二侧，以在第二基板中形成第二沟槽。 第二沟槽具有由隔离区域至少部分地限定的侧壁，并且第二沟槽露出第二绝缘层。 第二沟槽限定第一隔离区域（STI）上的第一有源区，并在绝缘层上限定第二有源区。 接下来，第二沟槽用绝缘体材料填充到第二隔离区域。 接下来，停止层被去除。 最后，在活动区域​​中形成器件。

公开(公告)号：US06468879B1

公开(公告)日：2002-10-22

申请号：US09807971

申请日：2001-08-13

申请人： Jean-Michel Lamure ,  François Lissalde

发明人： Jean-Michel Lamure ,  François Lissalde

IPC分类号： H01L2130

CPC分类号： B25B11/005 ,  B28D1/322 ,  B28D5/0005 ,  Y10S438/977 ,  Y10T83/0267 ,  Y10T83/2185 ,  Y10T83/748

摘要： The invention relates to a method of separating into two wafers (2,4) a plate (1) of material for manufacturing substrates for electronics, optics, or optoelectronics, or for manufacturing microsystems, said wafers being situated on either side of a plane of weakness (6), the method being characterized in that it comprises the steps consisting in: exerting a deformation force on at least one of the wafers so as to cause the wafers (2, 4) to separate from each other in a zone of the plate (1) at said plane of weakness; and exerting guided separation movement on the wafers (2, 4). The invention also provides apparatus (100) for implementing the method, which apparatus has gripping members (30, 32) suitable for exerting said deformation force and for performing said separation.

摘要翻译： 本发明涉及一种分离成用于制造用于电子学，光学或光电子学的衬底或用于制造微系统的材料的板（1）的两个晶片（2,4）的方法，所述晶片位于 所述方法的特征在于包括以下步骤：在至少一个晶片上施加变形力，以使晶片（2,4）在所述晶片（2）的区域中彼此分离 板（1）在所述弱点处; 本发明还提供了用于实施该方法的装置（100），该装置具有适于施加所述变形力并用于执行所述分离的夹持构件（30,32）。

公开(公告)号：US06436794B1

公开(公告)日：2002-08-20

申请号：US09860453

申请日：2001-05-21

申请人： Heon Lee ,  Chung-Ching Yang ,  Peter Hartwell

发明人： Heon Lee ,  Chung-Ching Yang ,  Peter Hartwell

IPC分类号： H01L2130

CPC分类号： G11B9/1436 ,  B81C1/00896 ,  B82Y10/00 ,  G01Q80/00 ,  G11B9/10 ,  G11B9/1463 ,  H01L21/68 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved process flow for an atomic resolution storage (ARS) system deposits conductive electrodes on a media side of a rotor wafer before wafer thinning process, i.e., grinding and CMP, thus protecting the conductive electrodes on a media surface from the grinding process. In addition, the CMOS circuitry is formed in a stator wafer at a relatively later stage. Therefore, the CMOS circuitry is less likely to be damaged by heat processing. In addition, some of the necessary processing may be performed with loosened thermal budget. Finally, because wafer bonding of the rotor wafer and the stator wafer is performed at a later stage, there is less probability of degradation of the wafer bonding. Accordingly, device yield may be enhanced, leading to lower manufacturing cost.

摘要翻译： 用于原子分辨率存储（ARS）系统的改进的工艺流程在晶片变薄处理（即研磨和CMP）之前在转子晶片的介质侧上沉积导电电极，从而保护介质表面上的导电电极免受研磨过程。 此外，CMOS电路在相对较晚的阶段形成在定子晶片中。 因此，CMOS电路不太可能被热处理所损坏。 另外，一些必要的处理可以用松散的热预算执行。 最后，由于转子晶片和定子晶片的晶片接合在稍后的阶段进行，所以晶片接合的劣化的可能性降低。 因此，可以提高装置产量，从而降低制造成本。

公开(公告)号：US06420244B1

公开(公告)日：2002-07-16

申请号：US09785329

申请日：2001-02-20

申请人： Chun-Chi Lee

发明人： Chun-Chi Lee

IPC分类号： H01L2130

摘要： A method for fabricating the wafer level chip scale package (WLCSP) is developed. This method mainly comprises the steps of: disposing a wafer on the top surface of a retractable film, the wafer having a plurality of chips and a plurality of cutting lines therebetween, each chip having a plurality of bonding pads; cutting the wafer into individual chips along the cutting lines; stretching the retractable film so as to separate the cut chips from one another with a predetermined distance; molding the cut wafer in order to encapsulate the bonding pads and sides of each chip completely; grinding the encapsulated chip to expose the bonding pads out of the molding compound; and sawing the encapsulated chips into individual semiconductor package unit.

公开(公告)号：US06407009B1

公开(公告)日：2002-06-18

申请号：US09190722

申请日：1998-11-12

申请人： Lu You ,  Dawn Hopper ,  Richard J. Huang

发明人： Lu You ,  Dawn Hopper ,  Richard J. Huang

IPC分类号： H01L2130

CPC分类号： H01L21/02134 ,  B05D1/005 ,  H01L21/02282 ,  H01L21/3124

摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.

摘要翻译： 本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。 改进的装置提供沉积室内的受控温度，压力和气体组成。 改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。 本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。 在一个实施方案中，前体溶液从晶片的外边缘向中心分配。 在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。 本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。 本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。 通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

公开(公告)号：US06406978B1

公开(公告)日：2002-06-18

申请号：US09715420

申请日：2000-11-18

申请人： Neng-Hui Yang ,  Ming-Sheng Yang ,  Chien-Mei Wang

发明人： Neng-Hui Yang ,  Ming-Sheng Yang ,  Chien-Mei Wang

IPC分类号： H01L2130

CPC分类号： C23C16/325 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/3185 ,  H01L21/32137 ,  Y10S438/931 ,  Y10S438/97

摘要： A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is formed on the dummy wafer as a base layer of the silicon carbid thin film. The silicon carbide thin film is then formed on the base layer. The property inspection of the silicon carbide thin film is performed. After the properties inspection, the silicon carbide is stripped using a high density hydrogen plasma. After the step of high density hydrogen plasma, if the remaining silicon nitride layer is thicker than about 500 angstroms, the remaining silicon nitride layer can be used as the base layer again for forming and inspecting the properties of the silicon carbide thin film. In contrast, if the remaining silicon nitride layer is thinner than about 500 angstroms, a acid solution is used to dip and remove the remaining silicon nitride layer, and the silicon wafer can then be recycled.

摘要翻译： 一种去除碳化硅的方法。 硅晶片用作伪晶片，用于检查将在其上形成的碳化硅薄膜的性质。 在作为硅碳化物薄膜的基底层的虚设晶片上形成厚度大于约1000埃的氮化硅层。 然后在基底层上形成碳化硅薄膜。 执行碳化硅薄膜的性能检查。 在进行性能检查后，使用高密度氢等离子体去除碳化硅。 在高密度氢等离子体的步骤之后，如果剩余的氮化硅层厚于约500埃，则剩余的氮化硅层可再次用作基底层，以形成和检查碳化硅薄膜的性质。 相比之下，如果剩余的氮化硅层比约500埃更薄，则使用酸溶液来浸渍和除去剩余的氮化硅层，然后可以再循环硅晶片。

公开(公告)号：US06383892B1

公开(公告)日：2002-05-07

申请号：US09225315

申请日：1999-01-05

申请人： John Z. Colt, Jr.

发明人： John Z. Colt, Jr.

IPC分类号： H01L2130

CPC分类号： H01L21/7624

摘要： An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

摘要翻译： 一种集成电路芯片，其中一个或多个半导体器件与同一电路中的其它半导体器件的本体效应完全隔离，以及制造集成电路芯片的方法。 这些器件可以是无源器件，例如电阻器或有源器件，例如二极管，双极晶体管或场效应晶体管（FET）。 多层半导体体优选由硅和二氧化硅形成。 在一个或多个层中形成导电区域或沟道。 对于FET，沟道区上方和下方的硅提供具有垂直对称器件特性的可控制栅极。 可以添加埋置的绝缘体层以将各个器件的下栅极彼此隔离并且产生多个垂直堆叠的隔离器件。 PFET和NFET器件都可以在耗尽和累积模式下以独立的掺杂分布形成。

公开(公告)号：US06383891B1

公开(公告)日：2002-05-07

申请号：US09284616

申请日：1999-06-24

申请人： Akira Okamoto

发明人： Akira Okamoto

IPC分类号： H01L2130

CPC分类号： H05K3/3468 ,  H01L21/4853 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/1147 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/044 ,  H05K2203/0545 ,  H05K2203/0746 ,  H05K2203/1581 ,  H05K2203/159 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

摘要： The present invention intends to form bumps of desired size and shape by simple steps. For this end, pads 2 are formed on a printed circuit board 1 at the same space as pads on a semiconductor chip 5. Then, the entire upper surface of the printed circuit board 1 is covered with a resist 3 except pad formed areas. The surface of the printed circuit board 1 covered with the resist 3 is then oriented downwardly and is sprayed with molten solder from the bottom side. The molten solder attaches the pad formed surface on the printed circuit board 1 and ideal semispherical bumps 4 are formed by the influence of gravity. The printed circuit board 1 formed with the bumps 4 is aligned with the pads 6 on the semiconductor chip 5 to be transferred into a high temperature oven. The bumps 4 are molten for jointing the semiconductor chip 5 and the printed circuit board 1.

摘要翻译： 本发明旨在通过简单的步骤形成所需尺寸和形状的凸块。 为此，焊盘2在与半导体芯片5上的焊盘相同的空间上形成在印刷电路板1上。然后，除了焊盘形成区域之外，印刷电路板1的整个上表面被抗蚀剂3覆盖。 然后，用抗蚀剂3覆盖的印刷电路板1的表面向下取向，并从底侧喷射熔融的焊料。 熔融焊料将焊盘形成的表面附着在印刷电路板1上，并且通过重力的影响形成理想的半球形凸块4。 形成有凸块4的印刷电路板1与半导体芯片5上的焊盘6对准，以转移到高温烘箱中。 为了接合半导体芯片5和印刷电路板1，熔融凸块4。