公开(公告)号：US20160329282A1

公开(公告)日：2016-11-10

申请号：US15110704

申请日：2014-02-11

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/525 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embedded fuse structures and fabrication techniques. An embedded fuse may include a non-planar conductive line having two high-z portions extending to a greater z-height than a low-z portion of reduced current carrying capability disposed there between. A dielectric disposed over the low-z portion has a top surface planar with the high-z line portions to which fuse contacts may be landed. Fabrication of an embedded fuse may include undercutting a region of a first dielectric material disposed over a substrate. The undercut region is lined with a second dielectric material. A pair of electrically joined fuse ends are formed by backfilling the lined undercut region with a conductive material. In advantageous embodiments, fuse fabrication is compatible with high-K, metal gate transistor and precision polysilicon resistor fabrication flows.

Abstract translation: 嵌入式熔断器结构和制造技术。 嵌入式保险丝可以包括非平面导电线，其具有延伸到比设置在其间的减小的载流能力的低z部分更大的z高的两个高z部分。 布置在低z部分上方的电介质具有与保险丝触点可能着陆的高z线部分平面的顶表面。 嵌入式保险丝的制造可以包括底切设置在衬底上的第一电介质材料的区域。 底切区域衬有第二介电材料。 一对电连接的保险丝端部用导电材料回填衬里的底切区域形成。 在有利的实施例中，熔丝制造与高K，金属栅极晶体管和精密多晶硅电阻器制造流程兼容。